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Preliminary Data Sheet December 2000
ORCA(R) Series 4 Field-Programmable Gate Arrays
Programmable Features
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High-performance platform design. -- 0.13 m seven-level metal technology. -- Internal performance of >250 MHz (four logic levels). -- I/O performance of >416 MHz for all user I/Os. -- Over 1.5 million usable system gates. -- Meets multiple I/O interface standards. -- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. -- Embedded block RAM (EBR) for onboard storage and buffer needs. -- Built-in system components including an internal system bus, eight PLLs, and microprocessor interface. Traditional I/O selections. -- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. -- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. -- Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. -- Two slew rates supported (fast and slew-limited). -- Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time.
-- Fast open-drain drive capability. -- Capability to register 3-state enable signal. -- Off-chip clock drive capability. -- Two-input function generator in output path.
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New programmable high-speed I/O. -- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR). -- Double-ended: LDVS, bused-LVDS, LVPECL. -- Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards. New capability to (de)multiplex I/O signals. -- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate). -- Used to implement emerging RapidIO backplane interface specification. -- New 2x and 4x downlink and uplink capability per I/O (i.e., 104 MHz internal to 416 MHz I/O). Enhanced twin-quad programmable function unit (PFU). -- Eight 16-bit look-up tables (LUTs) per PFU. -- Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations.
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* ZBT is a trademark of Integrated Device Technologies Inc. RapidIO is a trademark of Motorola, Inc.
Table 1. ORCA Series 4--Available FPGA Logic Device OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Columns 26 36 46 60 70 Rows 24 36 44 56 66 PFUs 624 1296 2024 3360 4620 User I/O 400 576 720 928 1088 LUTs 4992 10368 16,192 26,880 36,960 EBR Blocks 8 12 16 20 24 EBR Bits (k) 74 111 148 185 222 Usable Gates (k) 260--470 400--720 530--970 740--1350 930--1700
The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calculations. Note: Devices are not pinout compatible with ORCA Series 2/3.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Table of Contents
Contents Page Contents Page
Programmable Features............................................. 1 System Features .........................................................4 Product Description .....................................................6 Architecture Overview .............................................6 Programmable Logic Cells ..........................................7 Programmable Function Unit ...................................8 Look-Up Table Operating Modes ..........................11 Supplemental Logic and Interconnect Cell ............21 PLC Latches/Flip-Flops .........................................25 Embedded Block RAM ..............................................27 EBR Features ........................................................27 Routing Resources ...................................................31 Clock Distribution Network ........................................31 Primary Clock Nets ................................................31 Secondary Clock and Control Nets .......................31 Edge Clock Nets ....................................................31 Programmable Input/Output Cells .............................31 Programmable I/O .................................................31 Inputs .....................................................................34 Special Function Blocks ............................................38 Microprocessor Interface (MPI) .................................48 Embedded System Bus (ESB) ..................................49 Phase-Locked Loops.................................................52 FPGA States of Operation.........................................55 Initialization............................................................56 Configuration .........................................................56 Start-Up .................................................................56 Reconfiguration .....................................................60 Partial Reconfiguration ..........................................60 Other Configuration Options ..................................60 Bit Stream Error Checking .....................................62 FPGA Configuration Modes.......................................62 Master Parallel Mode.............................................63 Master Serial Mode ...............................................64 Asynchronous Peripheral Mode ............................65 Microprocessor Interface Mode .............................66 Slave Serial Mode .................................................70 Slave Parallel Mode...............................................70 Daisy Chaining ......................................................71 Daisy-Chaining with Boundary Scan .....................72 Absolute Maximum Ratings.......................................72 Recommended Operating Conditions .......................73 Electrical Characteristics ...........................................73 Pin Information ..........................................................75 Pin Descriptions.....................................................75 Package Compatibility ...........................................78 Package Thermal Characteristics Summary ...........118 JA ......................................................................118 JC ......................................................................118 Package Coplanarity ...............................................119 Package Parasitics ..................................................119 Package Outline Diagrams......................................120 Terms and Definitions..........................................120 Package Outline Drawings ......................................121 352-Pin PBGA .....................................................121 432-Pin EBGA .....................................................122 680-Pin PBGAM ..................................................123 Ordering Information................................................124
Figure
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JC......................................................................118 JB ......................................................................118
Package Thermal Characteristics............................119 2
Figure 1. Series 4 Top-Level Diagram ........................7 Figure 2. PFU Ports .....................................................9 Figure 3. Simplified PFU Diagram .............................10 Figure 4. Simplified F4 and F5 Logic Modes .............12 Figure 5. Simplified F6 Logic Modes .........................13 Figure 6. MUX 4 x 1...................................................13 Figure 7. MUX 8 x 1...................................................14 Figure 8. Softwired LUT Topology Examples.............15 Figure 9. Ripple Mode ...............................................16 Figure 10. Counter Submode ....................................17 Figure 11. Multiplier Submode...................................18 Figure 12. Memory Mode ..........................................19 Figure 13. Memory Mode Expansion Example--128 x 8 RAM ........................................21 Figure 14. SLIC All Modes Diagram ..........................22 Figure 15. Buffer Mode ..............................................23 Figure 16. Buffer-Buffer-Decoder Mode ....................23 Figure 17. Buffer-Decoder-Buffer Mode ....................24 Figure 18. Buffer-Decoder-Decoder Mode ................24 Figure 19. Decoder Mode..........................................25 Figure 20. Latch/FF Set/Reset Configurations ..........26 Figure 21. EBR Read and Write Cycles with Write Through ................................................29 Figure 22. Series 4 PIO Image from ORCA Foundry ......................................................33 Figure 23. ORCA High-Speed I/O Banks ..................36 Figure 24. PIO Shift Register.....................................38 Figure 25. Printed-Circuit Board with BoundaryScan Circuitry ........................................................39 Figure 26. Boundary-Scan Interface..........................40 Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram .................................43 Figure 28. TAP Controller State Transition Diagram .................................................................44 Figure 29. Boundary-Scan Cell .................................45 Figure 30. Instruction Register Scan Timing Diagram .................................................................46 Figure 31. PLL_VF External Requirements...............53 Figure 32. PLL Naming Scheme ...............................54 Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Table of Contents (continued)
Contents Page Contents Page
Figure 33. FPGA States of Operation ....................... 55 Figure 34. Initialization/Configuration/Start-Up Waveforms............................................................. 57 Figure 35. Start-Up Waveforms................................. 59 Figure 36. Serial Configuration Data Format--Autoincrement Mode .............................. 60 Figure 37. Serial Configuration Data Format--Explicit Mode .......................................... 60 Figure 38. Master Parallel Configuration Schematic ....................................... 63 Figure 39. Master Serial Configuration Schematic.... 65 Figure 40. Asynchronous Peripheral Configuration... 66 Figure 41. PowerPC/MPI Configuration Schematic... 67 Figure 42. Configuration Through MPI ...................... 68 Figure 43. Readback Through MPI ........................... 69 Figure 44. Slave Serial Configuration Schematic ...... 70 Figure 45. Slave Parallel Configuration Schematic ... 71 Figure 46. Daisy-Chain Configuration Schematic ..... 72 Figure 47. Package Parasitics ................................. 120 Table 17. PIO Logic Options..................................... 36 Table 18. Compatible Mixed I/O Standards .............. 36 Table 19. LVDS I/O Specifications........................... 37 Table 20. LVDS Termination Pin ............................. 37 Table 21. Dedicated Temperature Sensing.............. 39 Table 22. Boundary-Scan Instructions ..................... 40 Table 23. Series 4E Boundary-Scan Vendor-ID Codes................................................... 41 Table 24. TAP Controller Input/Outputs ................... 43 Table 25. Readback Options .................................... 46 Table 26. MPC 860 to ORCA MPI Interconnection .. 48 Table 27. Embedded System Bus/MPI Registers..... 50 Table 28. Interrupt Register Space Assignments ..... 50 Table 29. Status Register Space Assignments ........ 51 Table 30. Command Register Space Assignments .. 51 Table 31. PPLL Specifications.................................. 52 Table 32. DPLL DS-1/E-1 Specifications.................. 53 Table 33. Dedicated Pin Per Package ...................... 53 Table 34. STS-3/STM-1 DPLL Specifications........... 54 Table 35. Phase-Lock Loops Index .......................... 54 Table 36A. Configuration Frame Format and Contents ......................................................... 61 Table 36B. Configuration Frame Format and Contents for Embedded Block RAM............... 61 Table 37. Configuration Frame Size ......................... 62 Table 38. Configuration Modes................................. 63 Table 39. Absolute Maximum Ratings ...................... 73 Table 40. Recommended Operating Conditions....... 73 Table 41. Electrical Characteristics .......................... 73 Table 42. Pin Descriptions........................................ 75 Table 43. ORCA I/Os Summary ............................... 78 Table 44. 352-Pin PBGA Pinout ............................... 79 Table 45. 432-Pin EBGA .......................................... 89 Table 46. 680-Pin PBGAM Pinout ............................ 99 Table 47. ORCA Series 4 FPGAs Plastic Package Thermal Guidelines .............................. 119 Table 48. ORCA Series 4 FPGAs Package Parasitics .............................................. 119 Table 49. Series 4 Package Matrix (Speed Grades)................................................... 124 Table 50. Package Options..................................... 124
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Table 1. ORCA Series 4--Available FPGA Logic ....... 1 Table 2. System Performance .................................... 5 Table 3. Look-Up Table Operating Modes ................ 11 Table 4. Control Input Functionality .......................... 11 Table 5. Ripple Mode Equality Comparator Functions and Outputs .......................................... 18 Table 6. SLIC Modes ................................................ 22 Table 7. Configuration RAM Controlled Latch/ Flip-Flop Operation................................................ 25 Table 8. ORCA Series 4-- Available Embedded Block RAM .......................................... 27 Table 9. RAM Signals ............................................... 28 Table 10. FIFO Signals ............................................ 29 Table 11. Constant Multiplier Signals ....................... 30 Table 12. 8 x 8 Multiplier Signals.............................. 30 Table 13. CAM Signals ............................................. 30 Table 14. Series 4 Programmable I/O Standards ..... 32 Table 15. PIO Options .............................................. 35 Table 16. PIO Register Control Signals .................... 35
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
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Programmable Features (continued)
-- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. -- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4-to-1 MUX, new 8-to-1 MUX, and ripple mode arithmetic functions in the same PFU. -- 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the supplemental logic and interconnect cell (SLIC) decoders as bank drivers. -- Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. -- Flexible fast access to PFU inputs from routing. -- Fast-carry logic and routing to all four adjacent PFUs for nibble-, bytewide, or longer arithmetic functions, with the option to register the PFU carry-out.
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Built-in testability. -- Full boundary-scan (IEEE 2 1149.1 and Draft 1149.2 joint test access group (JTAG)). -- Programming and readback through boundaryscan port compliant to IEEE Draft 1532:D1.7. -- TS_ALL testability function to 3-state all I/O pins. -- New temperature-sensing diode used to determine device junction temperature.
System Features
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PCI local bus compliant. Improved PowerPC 3 860 and PowerPC II high-speed (66 MHz) synchronous MPI interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. New embedded AMBA4 specification 2.0 AHB system bus (ARM 4processor) facilitates communication among the microprocessor interface, configuration logic, EBR, FPGA logic, and embedded standard-cell blocks. Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard-cell blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. New network phase-locked loops (PLLs) meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications. Flexible general-purpose programmable PLLs offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. Improved built-in clock management with programmable phase-locked loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Each PPLL provides two separate clock outputs.
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Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-statable buffers, up to 10-bit decoder, and PAL1-like and-or-invert (AOI) in each programmable logic cell. New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: -- One 512 x 18 (quad-port, two read/two write) with optional built-in arbitration. -- One 256 x 36 (dual-port, one read/one write). -- One 1K x 9 (dual-port, one read/one write). -- Two 512 x 9 (dual-port, one read/one write for each). -- Two RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). -- Supports joining of RAM blocks. -- Two 16 x 8-bit content addressable memory (CAM) support. -- FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9. -- Constant multiply (8 x 16 or 16 x 8). -- Dual-variable multiply (8 x 8).
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1. PAL is a trademark of Advanced Micro Devices, Inc. 2. IEEE a is registered trademark of The Institute of Electrical and Electronics Engineers, Inc. 3. PowerPC is a registered trademark of International Business Machines, Corporation. 4. AMBA and ARM are trademarks of ARM Limited.
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
System Features (continued)
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Variable-size bused readback of configuration data capability with the built-in MPI and system bus. Internal, 3-state, bidirectional buses with simple control provided by the SLIC. Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed specifications for UTOPIA Level 4 for 10 Gbits/s interfaces. New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E4). New local clock routing structures allow creation of localized clock trees anywhere on the device. New DDR, QDR, and ZBT memory interfaces support the latest high-speed memory interfaces. New 2x/4x uplink and downlink I/O shift registers capabilities interface high-speed external I/Os to reduced internal logic speed. ORCA Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis.
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Table 2. System Performance Function 16-bit loadable up/down counter 16-bit accumulator 8 x 8 Parallel Multiplier Multiplier mode, unpipelined 1 ROM mode, unpipelined 2 Multiplier mode, pipelined 3 32 x 16 RAM (synchronous) Single port, 3-state bus 4 Dual-port 5 128 x 8 RAM (synchronous) Single port, 3-state bus 4 Dual-port, 3-state bus 5 Address Decode 8-bit internal, LUT-based 8-bit internal, SLIC-based 6 32-bit internal, LUT-based 32-bit internal, SLIC-based 7 36-bit Parity Check (internal) 0.25 0 2 0 2 1.37 0.73 4.68 2.08 4.68 ns ns ns ns ns 8 8 264 264 MHz MHz 4 4 264 340 MHz MHz 11.5 8 15 72 175 197 MHz MHz MHz No. PFUs 2 2 2 282 282 Unit MHz MHz
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain only pipelining registers). 4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus. 5. Implemented using 32 x 4 dual-port RAM mode. 6. Implemented in one partially occupied SLIC, with decoded output setup to CE in the same PLC. 7. Implemented in five partially occupied SLICs.
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. PICs provide the logical interface to the PIOs which provide the boundary interface off and onto the device. Also, the interquad routing blocks (hIQ, vIQ) separate the quadrants of the PLC array and provide the global routing and clocking elements. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. The Series 4 architecture integrates macrocell blocks of memory known as EBR. The blocks run horizontally across the PLC array and provide flexible memory functionality. Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. System-level functions such as a microprocessor interface, PLLs, embedded system bus elements (located in the corners of the array), the routing resources, and configuration RAM are also integrated elements of the architecture.
Product Description
Architecture Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lucent Technologies Microelectronics Group. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. The architecture consists of four basic elements: programmable logic cells (PLCs), programmable input/output cells (PIOs), embedded block RAMs (EBRs), and system-level features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs and its associated resources are surrounded by common interface blocks (CIBs) that provide an abundant interface to the adjacent PIOs or
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Product Description (continued)
EMBEDDED BLOCK RAM EMBEDDED MICROPROCESSOR INTERFACE (MPI) HIGH-SPEED I/Os
SYSTEM BUS
CLOCK PINS PFU
SLIC PLC PIO PIC
FPGA/SYSTEM BUS INTERFACE
PLLs
5-7536 (F)a
Figure 1. Series 4 Top-Level Diagram
Programmable Logic Cells
The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins with R3C2 in all Series 4 generic FPGAs. The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic functions. The PFU is the main logic element of the PLC, containing elements for both combinatorial
and sequential logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUTs twin-quad architecture provides a configurable medium-/large-grain architecture that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic functions using multiple LUTs. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per PFU while increasing system speed.
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
The PFU uses 36 data input lines for the LUTs, eight data input lines for the latches/FFs, eight control inputs (CLK[1:0], CE[1:0], LSR[1:0], SEL[1:0]), and a carry input (CIN) for fast arithmetic functions and generalpurpose data input for the ninth FF. There are eight combinatorial data outputs (one from each LUT), eight latched/registered outputs (one from each latch/FF), a carry-out (COUT), and a registered carry-out (REGCOUT) that comes from the ninth FF. The carry-out signals are used principally for fast arithmetic functions. There are also two dedicated F6 mode outputs which are for the 6-input LUT function and 8-to-1 MUX. Figure 2 and Figure 3 show high-level and detailed views of the ports in the PFU, respectively. The eight sets of LUT inputs are labeled as K0 through K7 with each of the four inputs to each LUT having a suffix of _x, where x is a number from 0 to 3. There are four F5 inputs labeled A through D. These are used for additional LUT inputs for 5- and 6-input LUTs or as a selector for multiplexing two 4-input LUTs. Four adjacent LUT4s can also be multiplexed together with a 4-to-1 MUX to create a 6-input LUT. The eight direct data inputs to the latches/FFs are labeled as DIN[7:0]. Registered LUT outputs are shown as Q[7:0], and combinatorial LUT outputs are labeled as F[7:0]. The PFU implements combinatorial logic in the LUTs and sequential logic in the latches/FFs. The LUTs are static random access memory (SRAM) and can be used for read/write or ROM. Each latch/FF can accept data from its associated LUT. Alternatively, the latches/FFs can accept direct data from DIN[7:0], eliminating the LUT delay if no combinatorial function is needed. Additionally, the CIN input can be used as a direct data source for the ninth FF. The LUT outputs can bypass the latches/FFs, which reduces the delay out of the PFU. It is possible to use the LUTs and latches/FFs more or less independently, allowing, for instance, a comparator function in the LUTs simultaneously with a shift register in the FFs.
Programmable Logic Cells (continued)
The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects with one available per set of quad FFs. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any 4-, 5-, or 6-input logic function and many multilevel logic functions using ORCA's SWL connections. In ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. In memory mode, the LUTs can be used as a 32 x 4 synchronous RAM or ROM, in either single- or dual-port mode. The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, true 3-state buses possible within the FPGA.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 53 external inputs and 20 outputs and can operate in several modes. The functionality of the inputs and outputs depends on the operating mode.
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIN F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 K0_3 F5A LSR[0:1] CLK[0:1] CE[0:1] SEL[0:1] F7 F6 F5 F4 F3 F2 F1 F0
LUT603 LUT647
PROGRAMMABLE FUNCTION UNIT (PFU)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 COUT REGCOUT
5-5752(F)a
Figure 2. PFU Ports
The PFU can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (RAM/ ROM) mode. In addition, ripple mode has four submodes and RAM mode can be used in either a single- or dualport memory fashion. These submodes of operation are discussed in the following sections.
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Programmable Logic Cells (continued)
FSDMUX F5D 0 K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C 0 SR1MODEATTR SR1MODE CE1_OVER_LSR1 LSR1_OVER_CE1 RSYNC1 CLK1 0 SEL1 0 CE1 1 LSR1 0 CIN 0 CLK0 0 SEL0 0 CE0 1 SR0MODEATTR SR0MODE CE0_OVER_LSR0 LSR0_OVER_CE0 ASYNC0 FSBMUX F5B 0 K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 K0_3 F5A 0 LOGIC MLOGIC RIPPLE RAM ROM PFU MODES GSR ENABLED DISABLED K3_0MUX A K3 B K3_2MUX C D K2_0MUX A K2 B K2_2MUX C D A K1 B C D A K0 B C D F5AMUX DIN0 0 DIN0MUX H1H0MUX LUT6MUX DIN2 0 DIN2MUX REG2 D0 D1 SD SP CK LSR H3H2MUX BMUX DIN3 0 DIN3MUX REG3 D0 D1 SD SP CK LSR Q3 RESET SET DEL0 DEL1 DEL2 DEL3 Q2 RESET SET DEL0 DEL1 DEL2 DEL3 LSR0 0 LSR0MUX 1 CE0MUX 1 SEL0MUX CEBMUX THIS IS ALWAYS A FLIPFLOP CLK0MUX CINMUX COUT LSR1MUX 0 LSR47MUX CE1MUX 1 CE47MUX SEL1MUX REGMODE_TOP FF LATCH REG 4 THROUGH 7 K7_0MUX A K7 B K7_2MUX C D K6_0MUX A K6 B K6_2MUX C D A K5 B C D A K4 B C D FSCMUX DIN4 0 CLK1MUX DIN4MUX H5H4MUX LUT6MUX DIN6 0 DIN6MUX REG6 D0 D1 SD SP CK LSR H7H6MUX AMUX DIN7 0 DIN7MUX REG7 D0 D1 SD SP CK LSR Q7 RESET SET DEL0 DEL1 DEL2 DEL3 Q6 RESET SET DEL0 DEL1 DEL2 DEL3
F7
F6
LUT647
F5
DIN5 0 DIN5MUX REG5 D0 D1 SD SP CK LSR REG4 D0 D1 SD SP CK LSR Q5 RESET SET DEL0 DEL1 DEL2 DEL3 Q4 RESET SET DEL0 DEL1 DEL2 DEL3
F4
0
CE03MUX REG8 D0 SP CK LSR RECCOUT RESET SET DEL0 DEL1 DEL2 DEL3
LSRBMUX
0
LSR03MUX
F3
F2
LUT603
F1
DIN1 0 DIN1MUX REG1 D0 D1 SD SP CK LSR REG0 D0 D1 SD SP CK LSR Q1 RESET SET DEL0 DEL1 DEL2 DEL3 Q0 RESET SET DEL0 DEL1 DEL2 DEL3
F0
REGMODE_BOT FF LATCH REG 0 THROUGH 3
5-9714(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram 10 Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode, the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT memory. Table 3 lists the basic operating modes of the LUT. Figure 4--Figure 7 show block diagrams of the LUT operating modes. The accompanying descriptions demonstrate each mode's use for generating logic. Table 3. Look-Up Table Operating Modes Mode Logic Function
4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to ninth FF or as pass through to COUT. Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; Half Ripple CIN and ninth FF for logic or ripple functions. Ripple All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. Memory All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as single-port or as ROM. PFU Control Inputs Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0], and their functionality for each logic mode of the PFU is shown in Table 4. The clock signal to the PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to the latches/FFs. All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs or the LUT outputs are always input to the latches/ FFs. Table 4. Control Input Functionality Mode Logic CLK[1:0] CLK to all latches/ FFs LSR[1:0] LSR to all latches/FFs, enabled per nibble and for ninth FF LSR to all latches/FF, enabled per nibble and for ninth FF LSR to all latches/FFs, enabled per nibble and for ninth FF LSR0 port enable 2 CE[1:0] CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF CE1 RAM write enable CE0 Port enable 1 Not used SEL[1:0] Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Not used Not used
Half Logic/ CLK to all latches/ Half Ripple FFs Ripple CLK to all latches/ FFs CLK to RAM
Memory (RAM) Memory (ROM)
Optional for Not used synchronous outputs
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Any combination of F4 and F5 LUTs is allowed per PFU using the eight 16-bit LUTs. Examples are eight F4 LUTs, four F5 LUTs, a combination of four F4 plus two F5 LUTs, a combination of two F4, one F5, plus one F6, or a combination of one F5, one MUX21 of two LUT4s, and one MUX41 of four LUT4s.
Programmable Logic Cells (continued)
Logic Mode The PFU diagram of Figure 3 represents the logic mode of operation. In logic mode, the eight LUTs are used individually or in flexible groups to implement user logic functions. The latches/FFs may be used in conjunction with the LUTs or separately with the direct PFU data inputs. There are three basic submodes of LUT operation in PFU logic mode: F4 mode, F5 mode, and the F6 mode. Combinations of the submodes are possible in each PFU. F4 mode, shown simplified in Figure 4, illustrates the uses of the basic 4-input LUTs in the PFU. The output of an F4 LUT can be passed out of the PFU, captured at the LUTs associated latch/FF, or multiplexed with the adjacent F4 LUT output using one of the F5[A:D] inputs to the PFU (not shown). Only adjacent LUT pairs (K0 and K1, K2 and K3, K4 and K5, K6 and K7) can be multiplexed, and the output always goes to the even-numbered output of the pair. The F5 submode of the LUT operation, shown simplified in Figure 4, indicates the use of 5-input LUTs to implement logic. 5-input LUTs are created from two 4-input LUTs and a multiplexer. The F5 LUT is the same as the multiplexing of two F4 LUTs described previously with the constraint that the inputs to both F4 LUTs be the same. The F5[A:D] input is then used as the fifth LUT input. The equations for the two F4 LUTs will differ by the assumed value for the F5[A:D] input, one F4 LUT assuming that the F5[A:D] input is zero, and the other assuming it is a one. The selection of the appropriate F4 LUT output in the F5 MUX by the F5[A:D] signal creates a 5-input LUT. Two 6-input LUTs are created by shorting together the inputs of four 4-input LUTs (K0:3 and K4:7) which are multiplexed together. The F5 inputs of the adjacent F4 LUTs derive the fifth and sixth inputs of the F6 mode as shown in Figure 5. The F6 outputs, LUT603 and LUT647, are dedicated to the F6 mode or can be used as the outputs of MUX8x1. MUX8x1 modes as shown in Figure 7 are created by programming adjacent 4-input LUTs to 2x1 MUXs and multiplexing down to create MUX8x1. Other functions can be implemented from the configuration shown in Figure 5 where the four LUT4s drive the 4x1 MUX in each half of the PFU if the LUT4 inputs are not tied to the same inputs. Both F6 mode and MUX8x1 are available in the upper and lower PFU nibbles.
K7
F7
K7_0 K7_1 K7_2 K7_3 F5D K6_0 K6_1 K6_2 K6_3
LUT4
LUT4
2x1 MUX
F6
K6
F6
K5
F5
K5_0 K5_1 K5_2 K5_3 F5C K4_0 K4_1 K4_2 K4_3
LUT4
K4
F4
LUT4
2x1 MUX
F4
K3
F3
K3_0 K3_1 K3_2 K3_3 F5B K2_0 K2_1 K2_2 K2_3
LUT4
K2
F2
LUT4
2x1 MUX
F2
K1
F1
K1_0 K1_1 K1_2 K1_3 F5A K0_0 K0_1 K0_2 K0_3
LUT4
K0
F0
LUT4
2x1 MUX
F0
5-9733(F)
Figure 4. Simplified F4 and F5 Logic Modes
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
K7_0 K7_1 K7_2 K7_0 K7_1 K7_2 K7_3 F5D K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 F5C K4_0 K4_1 K4_2 K4_3 LUT4 LUT4 K5_0 K5_1 K5_2 F5C K4_0 K4_1 K4_2 LUT4 2x1 MUX F3 F5D LUT4 K6_0 K6_1 K6_2 LUT4 2x1 MUX F4 LUT4
LUT4
4x1 MUX
LUT4
LUT647
K3_0 K3_1 K3_2 K3_3 F5B K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 F5A K0_0 K0_1 K0_2 K0_3
K3_0 K3_1 K3_2 LUT4 F5B K2_0 K2_1 K2_2 LUT4
LUT4
LUT4
2x1 MUX
F2
LUT4
4x1 MUX
LUT603
K1_0 K1_1 K1_2 F5A
LUT4
LUT4
K0_0 K0_1 K0_2
LUT4
2x1 MUX
F0
5-9734(F)a
5-9735(F)
Figure 5. Simplified F6 Logic Modes
Figure 6. MUX 4x1
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Programmable Logic Cells (continued)
K7_0 K7_1 K7_2 F5D K6_0 K6_1 K6_2
LUT4
LUT4
K5_0 K5_1 K5_2 F5C K4_0 K4_1 K4_2
4x1 MUX LUT4
MUX8x1 [LUT647]
LUT4
K3_0 K3_1 K3_2 F5B K2_0 K2_1 K2_2
LUT4
LUT4
K1_0 K1_1 K1_2 F5A K0_0 K0_1 K0_2
LUT4
4x1 MUX
MUX8x1 [LUT603]
LUT4
5-9736(F)a
Figure 7. MUX 8x1 Softwired LUT capability uses F4, F5, and F6 LUTs, along with MUX21 and MUX41 blocks together with internal PFU feedback routing, to generate complex logic functions up to three LUT levels deep. Multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs. In this manner, very complex logic functions, some of up to 22 inputs, can be implemented in a single PFU at greatly enhanced speeds. It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once, and PLC routing resources will not be required to use it in the larger equation.
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
F4 F4 F4 F4 F5 F5
F4
F4
F4
F4
F5
F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
TWO 9-INPUT FUNCTIONS IN ONE PFU
F5
F4
F4
F4
F4
F5
F5
F5
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
ONE 21-INPUT FUNCTION IN ONE PFU
5-5753 (F)
F4
F4
F4
3
F4
F4
F4
F4
F4
TWO 10-INPUT FUNCTIONS IN ONE PFU
ONE OF TWO 21-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F4
F5
F6
ONE 22-INPUT FUNCTION IN ONE PFU 6-INPUT LUT
5-5754 (F)
F4
4-INPUT LUT
F5
5-INPUT LUT
F6
Figure 8. Softwired LUT Topology Examples Lucent Technologies Inc. 15
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
operation (K3, F[3:0]), respectively. The ripple mode diagram (Figure 9) shows full PFU ripple operation, with half-logic ripple connections shown as dashed lines. The result output and ripple output are calculated by using generate/propagate circuitry. In ripple mode, the two operands are input into KZ[1] and KZ[0] of each LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see Figure 9). The ripple output from LUT K7/K3 can be routed on dedicated carry circuitry into any of four adjacent PLCs, and it can be placed on the PFU COUT/ FCOUT outputs. This allows the PLCs to be cascaded in the ripple mode so that nibblewide ripple functions can be expanded easily to any length. Result outputs and the carry-out may optionally be registered within the PFU. The capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelining in arithmetic functions.
Programmable Logic Cells (continued)
Half-Logic Mode Series 4 FPGAs are based upon a twin-quad architecture in the PFUs. The bytewide nature (eight LUTs, eight latches/FFs) may just as easily be viewed as two nibbles (two sets of four LUTs, four latches/FFs). The two nibbles of the PFU are organized so that any nibblewide feature (excluding some softwired LUT topologies) can be swapped with any other nibblewide feature in another PFU. This provides for very flexible use of logic and for extremely flexible routing. The half-logic mode of the PFU takes advantage of the twin-quad architecture and allows half of a PFU, K[7:4] and associated latches/FFs, to be used in logic mode while the other half of the PFU, K[3:0] and associated latches/FFs, is used in ripple mode. In half-logic mode, the ninth FF may be used as a general-purpose FF or as a register in the ripple mode carry chain. Ripple Mode The PFU LUTs can be combined to do bytewide ripple functions with high-speed carry logic. Each LUT has a dedicated carry-out net to route the carry to/from any adjacent LUT. Using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one PFU. Similarly, each PFU has carry-in (CIN, FCIN) and carry-out (COUT, FCOUT) ports for fast-carry routing between adjacent PFUs. The ripple mode is generally used in operations on two data buses. A single PFU can support an 8-bit ripple function. Data buses of 4 bits and less can use the nibblewide ripple chain that is available in half-logic mode. This nibblewide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. For example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one PFU in ripple mode (8 bits) and one PFU in half-logic mode (4 bits), freeing half of a PFU for general logic mode functions. Each LUT has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. A single bit is rippled from the previous LUT and is used as input into the current LUT. For LUT K0, the ripple input is from the PFU CIN or FCIN port. The CIN/FCIN data can come from either the fast-carry routing (FCIN) or the PFU input (CIN), or it can be tied to logic 1 or logic 0. In the following discussions, the notations LUT K7/K3 and F[7:0]/F[3:0] are used to denote the LUT that provides the carry-out and the data outputs for full PFU ripple operation (K7, F[7:0]) and half-logic ripple 16
C
DQ
REGOUT FCOUT
C K7[1] K7[0] K6[1] K6[0] K5[1] K5[0] K4[1] K4[0] K3[1] K3[0] K2[1] K2[0] K1[1] K1[0] K0[1] K0[0] IN/FCIN
COUT F7
K7
DQ
Q7 F6
K6
DQ
Q6 F5
K5
DQ
Q5 F4
K4
DQ
Q4 F3
K3
DQ
Q3 F2
K2
DQ
Q2 F1
K1
DQ
Q1 F0
K0
DQ
Q0
5-5755(F).
Figure 9. Ripple Mode
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate outputs. One of the three outputs selects whether the carry-in is to be propagated to the carry-out of the current LUT or if the carry-out needs to be generated. If the carry-out needs to be generated, this is provided by the second LUT output. The result of this selection is placed on the carry-out signal, which is connected to the next LUT carry-in or the COUT/FCOUT signal, if it is the last LUT (K7/K3). Both of these outputs can be any equation created from KZ[1] and KZ[0], but in this case, they have been set to the propagate and generate functions. The third LUT output creates the result bit for each LUT output connected to F[7:0]/F[3:0]. If an adder/subtractor is needed, the control signal to select addition or subtraction is input on F5A/F5C inputs. These inputs generate the controller input AS. When AS = 0, this function performs the adder, A + B. When AS = 1, the function performs the subtractor, A - B. The result bit is created in one-half of the LUT from a single bit from each input bus KZ[1:0], along with the ripple input bit. The second submode is the counter submode (see Figure 10). The present count, which may be initialized via the PFU DIN inputs to the latches/FFs, is supplied to input KZ[0], and then output F[7:0]/F[3:0] will either be incremented by one for an up counter or decremented by one for a down counter. If an up/down counter is needed, the control signal to select the direction (up or down) is input on F5A and F5C. When F5[A:C], respectively per nibble, is a logic 1, this indicates a down counter and a logic 0 indicates an up counter.
C DQ REGCOUT FCOUT C K7[0] K7 K6[0] K6 K5[0] K5 K4[0] K4 K3[0] K3 K2[0] K2 K1[0] K1 K0[0] K0 CIN/FCIN
5-5756(F)
COUT F7 DQ Q7 F6 DQ Q6 F5 DQ Q5 F4 DQ Q4 F3 DQ Q3 F2 DQ Q2 F1 DQ Q1 F0 DQ Q0
Figure 10. Counter Submode
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Programmable Logic Cells (continued)
In the third submode, multiplier submode, a single PFU can affect an 8x1 bit (4x1 for half-ripple mode) multiply and sum with a partial product (see Figure 11). The multiplier bit is input at F5[A:C], respectively per nibble, and the multiplicand bits are input at KZ[1], where K7[1] is the most significant bit (MSB). KZ[0] contains the partial product (or other input to be summed) from a previous stage. If F5[A:C] is logical 1, the multiplicand is added to the partial product. If F5[A:C] is logical 0, 0 is added to the partial product, which is the same as passing the partial product. CIN/FCIN can bring the carry-in from the less significant PFUs if the multiplicand is wider than 8 bits, and COUT/FCOUT holds any carry-out from the multiplication, which may then be used as part of the product or routed to another PFU in multiplier mode for multiplicand width expansion. Ripple mode's fourth submode features equality comparators. The functions that are explicitly available are A B, A B, and A B, where the value for A is input on KZ[0], and the value for B is input on KZ[1]. A value of 1 on the carry-out signals valid argument. For example, a carry-out equal to 1 in AB submode indicates that the value on KZ[0] is greater than or equal to the value on KZ[1]. Conversely, the functions A B, A + B, and A > B are available using the same functions but with a 0 output expected. For example, A > B with a 0 output indicates A B. Table 5 shows each function and the output expected. If larger than 8 bits, the carry-out signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. The use of this submode could be shown using Figure 9, except that the CIN/FCIN input for the least significant PFU is controlled via configuration. Table 5. Ripple Mode Equality Comparator Functions and Outputs Equality Function AB AB AB AB A=B ORCA Foundry Submode AB AB AB A>B AC DQ REGCOUT
F5[A:C] C K7[1] 0 K7[0] K6[1] 0 K6[0] K5[1] 0 K5[0] K4[1] 0 K4[0] K3[1] 0 K3[0] K2[1] 0 K2[0] K1[1] 0 K1[0] K0[1] 0 K0[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 F7 + K7 F6 + K6 F5 + K5 F4 + K4 F3 + K3 F2 + K2 F1 + K1 F0 + K0 D Q Q0 D Q Q1 D Q Q2 D Q Q3 D Q Q4 D Q Q5 D Q Q6 D Q Q7
COUT
5-5757(F)
Key: C = configuration data. Note: F5[A:C] shorted together.
Figure 11. Multiplier Submode
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
Memory Mode The Series 4 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port RAM. A block diagram of a PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM.
F5[A:D] KZ[3:0] CIN(WA1) DQ 4 5
READ ADDRESS[4:0] WRITE ADDRESS[4:0]
DIN7(WA3)
DQ F6 F4 F2 F0
DIN5(WA2)
DQ
DQ DIN3(WA1) DQ DQ DIN1(WA0) DQ READ DATA[3:0] 4
Q6
Q4
DQ DIN6(WD3) DQ 4 WRITE DATA[3:0] DQ DIN4(WD2) DQ
Q2
Q0
DIN2(WD1)
DQ
DIN0(WD0)
DQ
CE0, LSR0 (SEE NOTE 2.) CE1
DQ S/E
WRITE ENABLE RAM CLOCK
CLK[0:1]
5-5969(F)a
1. CLK[0:1] are commonly connected in memory mode. 2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled). CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1. LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.
Figure 12. Memory Mode Lucent Technologies Inc. 19
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Wider memories can be created by operating two or more memory mode PFUs in parallel, all with the same address and control signals, but each with a different nibble of data. To increase memory word depth above 32, two or more PLCs can be used. Figure 10 shows a 128 x 8 dual-port RAM that is implemented in eight PLCs. This figure demonstrates data path width expansion by placing two memories in parallel to achieve an 8-bit data path. Depth expansion is applied to achieve 128 words deep using the 32-word deep PFU memories. In addition to the PFU in each PLC, the SLIC (described in the next section) in each PLC is used for read address decodes and 3-state drivers. The 128 x 8 RAM shown could be made to operate as a single-port RAM by tying (bit-for-bit) the read and write addresses. To achieve depth expansion, one or two of the write address bits (generally the MSBs) are routed to the write port enables as in Figure 10. For 2 bits, the bits select which 32-word bank of RAM of the four available from a decode of two WPE inputs is to be written. Similarly, 2 bits of the read address are decoded in the SLIC and are used to control the 3-state buffers through which the read data passes. The write data bus is common, with separate nibbles for width expansion, across all PLCs, and the read data bus is common (again, with separate nibbles) to all PLCs at the output of the 3-state buffers. Figure 13 also shows the capability to provide a read enable for RAMs/ROMs using the SLIC cell. The read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired.
Programmable Logic Cells (continued)
The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 12. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable controlling ports are input on CE0, CE1, and LSR0. CE1 is the activehigh write enable (CE1 = 1, RAM is write enabled). The first write port is enabled by CE0. The second write port is enabled with LSR0. The PFU CLK (CLK0) signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next clock edge one-half cycle later. The read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. If the read and write address lines are tied together (maintaining MSB to MSB, etc.), then the dual-port RAM operates as a synchronous single-port RAM. If the write enable is disabled, and an initial memory contents are provided at configuration time, the memory acts as a ROM (the write data and write address ports and write port enables are not used).
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
WD[7:0] 8 4 PLC 4 PLC 4 PLC 4 PLC
WD[7:4] 5 WA WPE 1 WPE 2 WE RD[7:4] RA 5 5
WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5 5
WD[7:4] WA WPE 1 WPE 2 WE RD[7:4] RA 5 5
WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5
RE 4 RD[7:0] WE WA[6:0] RA[6:0] CLK RE 7 7 8 4
RE 4
RE 4
RE
5-5749(F)
Figure 13. Memory Mode Expansion Example--128 x 8 RAM
Supplemental Logic and Interconnect Cell
Each PLC contains a SLIC embedded within the PLC routing, outside of the PFU. As its name indicates, the SLIC performs both logic and interconnect (routing) functions. Its main features are 3-statable, bidirectional buffers, and a PAL-like decoder capability. Figure 14 shows a diagram of a SLIC with all of its features shown. All modes of the SLIC are not available at one time. The ten SLIC inputs can be sourced directly from the PFU or from the general routing fabric. SI[0:9] inputs can come from the horizontal or vertical routing, and I[0:9} comes from the PFU outputs O[9:0]. These inputs can also be tied to a logical 1 or 0 constant. The inputs are twin-quad in nature and are segregated into two groups of four nibbles and a third group of two inputs for control. Each input nibble groups also have 3-state capability; however, the third pair does not. There is one 3-state control (TRI) for each SLIC, with the capability to invert or disable the 3-state control for each group of four BIDIs. Separate 3-state control for each nibblewide group is achievable by using the SLICs decoder (DEC) output, driven by the group of Lucent Technologies Inc.
two BIDIs, to control the 3-state of one BIDI nibble while using the TRI signal to control the 3-state of the other BIDI nibble. Figure 15 shows the SLIC in buffer mode with available 3-state control from the TRI and DEC signals. If the entire SLIC is acting in a buffer capacity, the DEC output may be used to generate a constant logic 1 (VHI) or logic 0 (VLO) signal for general use. The SLIC may also be used to generate PAL-like ANDOR with optional INVERT (AOI) functions or a decoder of up to 10 bits. Each group of buffers can feed into an AND gate (4-input AND for the nibble groups and 2-input AND for the other two buffers). These AND gates then feed into a 3-input gate that can be configured as either an AND gate or an OR gate. The output of the 3-input gate is invertible and is output at the DEC output of the SLIC. Figure 19 shows the SLIC in full decoder mode. The functionality of the SLIC is parsed by the two nibblewide groups and the 2-bit buffer group. Each of these groups may operate independently as BIDI buffers (with or without 3-state capability for the nibblewide groups) or as a PAL/decoder.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Programmable Logic Cells (continued)
As discussed in the Memory Mode section on page 19, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC. Figure 15--Figure 19 show several configurations of the SLIC, while Table 6 shows all of the possible modes. Table 6. SLIC Modes Mode No. 1 2 3 4 5 6 7 8 Mode BUFFER BUF_BUF_DEC BUF_DEC_BUF BUF_DEC_DEC DEC_BUF_BUF DEC_BUF_DEC DEC_DEC_BUF DECODER BUF [3:0] Buffer Buffer Buffer Buffer Decoder Decoder Decoder Decoder BUF [7:4] Buffer Buffer Decoder Decoder Buffer Buffer Decoder Decoder BUF [9:8] Buffer Decoder Buffer Decoder Buffer Decoder Buffer Decoder
SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SOUT08 SOUT09
SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 TRI 0/1 DEC 0/1 0/1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 0/1
SOUT07
SOUT06
SOUT05 DEC SOUT04
SOUT03
SOUT02
SOUT01
SOUT00
5-5744(F).a.
Figure 14. SLIC All Modes Diagram
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Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
SIN9 I9 SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 1 TRI 0/1 1 0 THIS CAN BE USED TO GENERATE A VHI OR VLO. 0/1 SIN3 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0
5-5745(F).a
SOUT09
LOGIC 1 OR 0 SIN8 I8
SOUT08
LOGIC 1 OR 0
I7 SOUT07 LOGIC 1 OR 0 SIN6 I6 SOUT06 LOGIC 1 OR 0 SIN5 I5 SOUT05 LOGIC 1 OR 0 SIN4 I4 SOUT04 LOGIC 1 OR 0
SOUT07
SOUT06
SOUT05
SOUT04
DEC TRI 1 DEC 1
1 I3 SOUT03 LOGIC 1 OR 0 SIN2 I2 SOUT02 LOGIC 1 OR 0 SIN1 I1 SOUT01 LOGIC 1 OR 0 SIN0 I0 SOUT00 LOGIC 1 OR 0
5-5746(F).a
SOUT03
SOUT02
SOUT01
SOUT00
Figure 16. Buffer-Buffer-Decoder Mode
Figure 15. Buffer Mode
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Programmable Logic Cells (continued)
SIN9
SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SOUT08 SOUT09
LOGIC 1 OR 0 SIN8
LOGIC 1 OR 0
SIN7
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN4
LOGIC 1 OR 0
LOGIC 1 OR 0
DEC
SIN4
TRI
LOGIC 1 OR 0
1
TRI
DEC
1 SIN3 I3 SOUT03 IF LOW, THEN 3-STATE BUFFERS ARE HIGH Z.
1
LOGIC 1 OR 0 SIN2
1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0
5-5747(F).a
I2 LOGIC 1 OR 0
SOUT02
SOUT03
SIN1 I1 LOGIC 1 OR 0 SIN0 SOUT01
SOUT02
I0 LOGIC 1 OR 0
SOUT00
5-5750(F).a
SOUT01
Figure 18. Buffer-Decoder-Decoder Mode
SOUT00
Figure 17. Buffer-Decoder-Buffer Mode
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Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
PLC Latches/Flip-Flops
The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some apply to the latches/FFs on a nibblewide basis where the ninth FF is considered independently. For other options, each latch/FF is independently programmable. In addition, the ninth FF can be used for a variety of functions. Table 7 summarizes these latch/FF options. The latches/FFs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered FFs (the ninth register can only be a FF). All latches/FFs in a given nibble of a PFU share the same clock, and the clock to these latches/FFs can be inverted. The input into each latch/FF is from either the corresponding LUT output (F[7:0]) or the direct data input (DIN[7:0]). The latch/FF input can also be tied to logic 1 or to logic 0, which is the default. Table 7. Configuration RAM Controlled Latch/ Flip-Flop Operation Function Options
Programmable Logic Cells (continued)
SIN9
LOGIC 1 OR 0 SIN8
LOGIC 1 OR 0
SIN7
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN4
LOGIC 1 OR 0 DEC
SIN3
LOGIC 1 OR 0 SIN2
LOGIC 1 OR 0 SIN1
LOGIC 1 OR 0 SIN0
LOGIC 1 OR 0
5-5748(F)
Common to All Latches/FFs in PFU Enable GSRN GSRN enabled or has no effect on PFU latches/FFs. Set Individually in Each Latch/FF in PFU Set/Reset Mode Set or reset. By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8]) Clock Enable CE or none. LSR Control LSR or none. Clock Polarity Noninverted or inverted. Latch/FF Mode Latch or FF. LSR Operation Asynchronous or synchronous. Front-end Select* Direct (DIN[7:0]) or from LUT (F[7:0]). LSR Priority Either LSR or CE has priority.
* Not available for FF[8].
Figure 19. Decoder Mode Each PFU has two independent programmable clocks, clock enable CE[1:0], local set/reset LSR[1:0], and front-end data selects SEL[1:0]. When CE is disabled, each latch/FF retains its previous value when clocked. The clock enable, LSR, and SEL inputs can be inverted to be active-low.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
F[7:0], or direct from DIN[7:0], bypassing the LUT. In the front-end data select mode, both signals are available to the latches/FFs. If either or both of these inputs is unused or is unavailable, the latch/FF data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). The latches/FFs can be configured in three basic modes:
s
Programmable Logic Cells (continued)
The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the GSRN and local set/reset (LSR) signals are not asserted, the latch/FF operates normally. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous, LSR has the option to be enabled only if clock enable (CE) is active or for LSR to have priority over the clock enable input, thereby setting/resetting the FF independent of the state of the clock enable. The clock enable is supported on FFs, not latches. It is implemented by using a 2-input multiplexer on the FF input, with one input being the previous state of the FF and the other input being the new data applied to the FF. The select of this 2-input multiplexer is clock enable (CE), which selects either the new data or the previous state. When the clock enable is inactive, the FF output does not change when the clock edge arrives. The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN and LSR are set or reset inputs. The set/reset value is independent for each latch/FF. An option is available to disable the GSRN function per PFU after initial device configuration. The latch/FF can be configured to have a data frontend select. Two data inputs are possible in the frontend select mode, with the SEL signal used to select which data input is used. The data input into each latch/FF is from the output of its associated LUT,
Local synchronous set/reset: the input into the PFU's LSR port is used to synchronously set or reset each latch/FF. Local asynchronous set/reset: the input into LSR asynchronously sets or resets each latch/FF. Latch/FF with front-end select, LSR either synchronous or asynchronous: the data select signal selects the input into the latches/FFs between the LUT output and direct data in.
s
s
For all three modes, each latch/FF can be independently programmed as either set or reset. Figure 20 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. The ninth PFU FF, which is generally associated with registering the carry-out signal in ripple mode functions, can be used as a general-purpose FF. It is only an FF and is not capable of being configured as a latch. Because the ninth FF is not associated with an LUT, there is no front-end data select. The data input to the ninth FF is limited to the CIN input, logic 1, logic 0, or the carry-out in ripple and half-logic modes.
CE F DIN LOGIC 1 LOGIC 0 LSR S_RESET CLK SET RESET GSRN CD CD GSRN LSR CE D S_SET Q F DIN LOGIC 1 LOGIC 0
CE CE D Q
F DIN LOGIC 1 LOGIC 0
SEL D DIN
CE CE Q
CLK SET RESET
GSRN LSR
CLK SET RESET
CD
5-9737(F).a
Key: CD = configuration data.
Figure 20. Latch/FF Set/Reset Configurations
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Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
s
Embedded Block RAM
The ORCA Series 4 devices complement the distributed PFU RAM with large blocks of memory macrocells. The memory is available in 512 words by 18 bits/ word blocks with two write and two read ports. Two byte lane enables also operate with quad-port functionality. Additional logic has been incorporated for FIFO, multiplier, and CAM implementations. The RAM blocks are organized along the PLC rows and are added in proportion to the FPGA array sizes as shown in Table 8. The contents of the RAM blocks may be optionally initialized during FPGA configuration. Table 8. ORCA Series 4-- Available Embedded Block RAM
Device OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Number of Blocks 8 12 16 20 24 Number of EBR Bits 74K 111K 148K 185K 222K
Two 512 x 9 built in one EBR with two separate read, write clocks and enables for independent operation. Two RAMs with a user customized number of words whose sum is 512 (or less) by 18.
s
The joining of RAM blocks is supported to create wider and deeper memories. The adjacent routing interface provided by the CIBs allow the cascading of blocks together with minimal penalties due to routing delays. FIFO Modes FIFOs can be configured to 256, 512, or 1K depths and 36, 18, or 9 widths respectively or two-512 x 9 but also can be expanded using multiple blocks. FIFO works synchronously with the same read and write clock where the read port can be registered on the output or not registered. It can also be optionally configured asynchronously with different read and write clocks. Integrated flags allow the user the ability to fully utilize the EBR for FIFO, without the need to dedicate an address for providing distinct full/empty status. There are four programmable flags provided for each FIFO: Empty, partially empty, full, and partially full FIFO status. The partially empty and partially full flags are programmable with the flexibility to program the flags to any value from the full or empty threshold. The programmed values can be set to a fixed value through the bit stream, or a dynamic value can be controlled by input pins of the EBR FIFO. Multiplier Modes The ORCA EBR supports two variations of multiplier functions. Constant coefficient MULTIPLY [KCM] mode will produce a 24-bit output of a fixed 8-bit constant multiply of a 16-bit number or a fixed 16-bit constant multiply of an 8-bit number. This KCM multiplies a constant times a 16- or 8-bit number and produces a product as a 24-bit result. The coefficient and multiplication tables are stored in memory. Both the input and outputs can be configured to be registered for pipelining. Both write ports are available during MULTIPLY mode so that the user logic can update and modify the coefficients for dynamic coefficient updates. An 8 x 8 MULTIPLY mode is configurable to either a pipelined or combinatorial multiplier function of two 8-bit numbers. Two 8-bit operands are multiplied to yield a 16-bit product. The input and outputs can be registered in pipeline mode.
Each highly flexible 512 x 18 (quad-port, two read/two write) RAM block can be programmed by the user to meet their particular function. Each of the EBR configurations use the physical signals as shown in Table 9. Quad-port addressing permits simultaneous read and write operations. The EBR ports are written synchronously on the positive edge of CKW. Synchronous read operations use the positive edge of CKR. Options are available to use synchronous read address registers and read output registers, or to bypass these registers and have the RAM read operate asynchronously.
EBR Features
Quad-Port Modes (Two Read/Two Write)
s
512 x 18 with optional built-in arbitration between write ports. 1024 x 18 built on two blocks with built-in decode logic for simplified implementation and increased speed.
s
Dual-Port Modes (One Read/One Write)
s s
One 256 x 36. One 1K x 9.
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Preliminary Data Sheet December 2000
Arbitration logic is optionally programmed by the user to signal occurrences of data collisions as well as to block both ports from writing at the same time. The arbitration logic prioritizes PORT1. When utilizing the arbiter, the signal BUSY indicates data is being written to PORT1. This BUSY output signals PORT1 activity by driving a high output. The arbitration default is enabled; however, the user may disable the arbiter in configuration. If the arbiter is turned off, both ports could be written at the same time and the data would be corrupt. In this scenario, the BUSY signal will indicate a possible error. There is also a user option which dedicates PORT 1 to communications to the system bus. In this mode, the user logic only has access to PORT0 and arbitration logic is enabled. The system bus utilizes the priority given to it by the arbiter; therefore, the system bus will always be able to write to the EBR.
Embedded Block RAM (continued)
CAM Mode The CAM block is a content address memory that provides fast address searches by receiving data input and returning addresses that contain the data. Implemented in each EBR are two 16-word x 8-bit CAM function blocks. The CAM has three modes: single match, multiple match, and clear, which are all achieved in one clock cycle. In single-match mode, an 8-bit data input is internally decoded and reports a match when data is present in a particular RAM address. Its result is reported by a corresponding single address bit. In multiple match, the same occurs with the exception of multiple address lines report the match. Clear mode is used to clear the CAM contents in one clock cycle by erasing all locations.) Table 9. RAM Signals
Port Signals PORT 0 AR0[#:0] AW0[#:0] BW0<1:0> I I I I/O
Function
CKR0 CKW0 CSR0 CSW0 D [#:0] Q [#:0] PORT 1 AR1[#:0] AW1[#:0] BW1<1:0>
I I I I I O I I I
Address to be read. Address to be written. Byte-write enable. Byte = 8 bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active-high. Enables write to occur. Active-high. Input data to be written to RAM. Output data of memory contents at referenced address. Address to be read. Address to be written. Byte-write enable. Byte = 8 bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active-high. Enables write to occur. Active-high. Input data to be written to RAM. Output data of memory contents at referenced address. PORT1 writing. Active-high. Data output registers cleared. Memory contents unaffected. Active-low.
CKR1 CKW1 CSR1 CSW1 D [#:0] Q [#:0] Control BUSY RESET
I I I I I O O I
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Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Embedded Block RAM (continued)
CKWPL CKW CSWSU CSW AWSU AW DSU D BWSU BW d c
CKWPH
CSWH
AWH
DH
BWH
AR
a AQH
b
c AQ b c CKWQ d
0308 (F)
Q
a
Figure 21. EBR Read and Write Cycles with Write Through Table 10. FIFO Signals Port Signals AR(1:0)[9:0] AW(1:0)[9:0] FF PFF PEF EF D0[17:0] D1[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] RESET Q0[17:0] Q1[17:0] I/O I I O O O O I I I I I I I O O Function Programs FIFO flags. Used for partially empty flag size. Programs FIFO flags. Used for partially full flag size. Full flag. Partially full flag. Partially empty flag. Empty flag. Data inputs for all configurations. Data inputs for 256 x 36 configurations only. Positive-edge write port clock. Port 1 only used for 256 x 36 configurations. Positive-edge read port clock. Port 1 only used for 256 x 36 configurations. Active-high write enable. Port 1 only used for 256 x 36 configurations. Active-high read enable. Port 1 only used for 256 x 36 configurations. Active-low. Resets FIFO pointers. Data outputs for all configurations. Data outputs for 256 x 36 configurations.
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Preliminary Data Sheet December 2000
Embedded Block RAM (continued)
Table 11. Constant Multiplier Signals Port Signals AR0[15:0] AW(1:0)[8:0] D(1:0)[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] Q[23:0] I/O I I I I I I I O Function Data input--operand. Address bits. Data inputs to load memory or change coefficient. Positive-edge write port clock. Positive-edge read port clock. Used for synchronous multiply mode. Active-high write enable. Active-high read enable. Data outputs--product result.
Table 12. 8 x 8 Multiplier Signals Port Signals AR0[7:0] AR1[7:0] AW(1:0)[8:0] D(1:0)[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] BW(1:0)[1:0] Q[15:0] Table 13. CAM Signals Port Signals AR(1:0)[7:0] AW(1:0)[8:0] D(1:0)[17] D(1:0)[16] D(1:0)[3:0] CSW[1:0] CSR[1:0] Q(1:0)15:0] I/O I I I I I I I O Function Data match. Data write. Clear data active-high. Single match active-high. CAM address for data write. Active-high write enable. Enable for CAM data write. Active-high enable data registers. Enable for CAM data registers. Decoded data outputs. 1 corresponds to a data match at that address location. I/O I I I I I I I I I O Function Data input--multiplicand. Data input--multiplier. Address bits for memory. Data inputs to load memory. Positive-edge write port clock. Positive-edge read port clock. Used for synchronous multiply mode. Active-high write enable. Active-high enables. For enabling address registers. Byte-lane write for loading memory. Data outputs--product.
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ORCA Series 4 FPGAs
located in the center of each side of the device, from the programmable PLLs, and dedicated network PLLs located in the corners, or from PLC logic. The I/O pads are dedicated in pairs for use of differential I/O clocking or single-ended I/O clock sources. However, if these pads are not needed to source the clock network, they can be utilized for general I/O. The clock routing scheme is patterned using vertical and horizontal routes which provide connectivity to all PLC columns.
Routing Resources
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. x1 routes cross width of one PLC and provide local connectivity to PFU and SLIC inputs and outputs. x6 lines cross width of six PLCs and are unidirectional and buffered with taps in the middle and on the end. Segments allow connectivity to PFU/SLIC outputs (driven at one endpoint), other x6 lines (at endpoints), and x1 lines for access to PFU/SLIC inputs. xH lines run vertically and horizontally the distance of half the device and are useful for driving medium-/long-distance 3-state routing. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds even when the I/O signals have been locked to specific pins. Generally, the ORCA Foundry Development System is used to automatically route interconnections. Interactive routing with the ORCA Foundry design editor (EPIC) is also available for design optimization. The routing resources consist of switching circuitry and metal interconnect segments. Generally, the metal lines which carry the signals are designated as routing segments. The switching circuitry connects the routing segments, providing one or more of three basic functions: signal switching, amplification, and isolation. A net running from a PFU or PIO output (source) to a PLC or PIO input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (CIPs).
Secondary Clock and Control Nets
Secondary spines provide flexible clocking and control signaling for local regions. Secondary nets usually have high fan-outs. The Series 4 utilizes a spine and branches that use additional x6 segments. This strategy provides a flexible connectivity and routes can be sourced from any I/O pin, all PLLs, or from PLC logic.
Edge Clock Nets
Routes are distributed around the edges and are available for every four PIOs (one per PIC). All PIOs and PLLs can drive the edge clocks and are used in conjunction with the secondary spines discussed above to drive the same edge clock signal into the internal logic array. The edge clocks provide fast injection to the PLC array and I/O registers. Many edge clock nets are provided on each side of the device.
Programmable Input/Output Cells
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/O that meets system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices with the addition of new features that allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIC contains up to four programmable I/O pads and are interfaced through a common interface block to the FPGA array. The PIO group is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/FF which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. 31
Clock Distribution Network
Primary Clock Nets
The Series 4 FPGAs provide eight fully distributed global primary net routing resources. These eight primary nets can only drive clock signals. The scheme dedicates four of the eight resources to provide fast primary nets and four are available for general primary nets. The fast primary nets are targeted toward low-skew and small injection times while the general primary nets are also targeted toward low-skew but have more source location flexibility. Fast access to the global primary nets can be sourced from two pairs of pads Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os that meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed singleended and differential pair signaling (as shown in Table 14). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V output levels.
Programmable Input/Output Cells
(continued) On the output side of each PIO, an output from the PLC array can be routed to each output FF, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered.
Table 14. Series 4 Programmable I/O Standards Standard LVTTL LVCMOS2 LVCMOS1.8 PCI LVDS Bused-LVDS LVPECL PECL GTL GTL+ HSTL-Class I HTSL-Class III and IV STTL3-Class I and II SSTL2-Class I and II VDDIO (V) VREF (V) 3.3 2.5 1.8 3.3 2.5 2.5 2.5 3.3 3.3 3.3 1.5 1.5 3.3 2.5 NA NA NA NA NA NA NA 2.0 0.8 1.0 0.75 0.9 1.5 1.25 General purpose. Interface Usage
PCI. Point to point and multidrop backplanes, high noise immunity. Network backplanes, high noise immunity, bus architecture backplanes. Network backplanes, differential 100 MHz+ clocking, optical transceiver, high-speed networking. Backplanes. Backplane or processor interface. High-speed SRAM and networking interfaces. Synchronous DRAM interface.
Note: Interfaces to DDR and ZBT memories are supported through the interface standards shown above.
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ORCA Series 4 FPGAs
The I/O on the OR4Exxx Series devices allows compliance with PCI Local Bus (Rev. 2.2) 3.3 V signaling environments. The signaling environment used for each input buffer can be selected on a per-pin basis. The selection provides the appropriate I/O clamping diodes for PCI compliance. The CIBs that bound the PIOs have significant local routing resources, similar to routing in the PLCs. This new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. The flexibility provided by the routing also provides for increased signal speed due to a greater variety of optimal signal paths. Included in the PIO routing interface is a fast path from the input pins to the PFU logic. This feature allows for input signals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA. Also, the Series 4 PIOs include latches and FFs and options for using fast, dedicated secondary, and edge clocks. A diagram of a single PIO is shown in Figure 22, and Table 15 provides an overview of the programmable functions in an I/O cell.
Programmable Input/Output Cells
(continued) The PIOs are located along the perimeter of the device. The PIO name is represented by a two-letter designation to indicate on which side of the device it is located followed by a number to indicate in which row or column it is located. The first letter, P designates that the cell is , a PIO and not a PLC. The second letter indicates the side of the array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth row. Each PIC interfaces to four bond pads and contains the necessary routing resources to provide an interface between I/O pads and the PLCs. Each PIC is composed of four programmable I/Os and significant routing resources. Each PIC contains input buffers, output buffers, routing resources, latches/FFs, and logic and can be configured as an input, output, or bidirectional I/O. Any PIO is capable of supporting the I/O standard listed in Table 12 and supporting DDR and ZBT specifications.
RESISTOR LEVELMODE OUTPUT SIDE LVTTL LVCMOS2 OUTSH OUTDD CLK AND NAND OR NOR XOR XNOR OUTDDMUX OUTDD 0 OUTFFMUX OUTFF 0 EC SC CE CEMUX0 CLK4MUX DEL0 DEL1 DEL2 DEL3 OUTREG OUTREG DO CK SP LSR 1 LSRMUX LSR 0 GSR ENABLED DISABLED CE_OVER_LSR LSR_OVER_CE ASYNC 5-9732(F) SRMODE RESET SET LATCH FF P2MUX OUTDD USRTS TSREG 1 DO CK LSR RESET SET 0 OUTSH PMUX OUTMUX OUTSHMUX CLK OUTDD TSMUX IOPAD CE PULLMODE UP DOWN NONE 1 CEMUXI EC SC NORMAL INVERTED PLOGIC BUFMODE SLEW FAST NA LVCMOS18 PCI SSTL2 SSTL3 HSTL1 HSTL3 GTL GTLPLUS PECL LVPECL LVDS DELAY CELL INMUX D0 CK D1 CK SP DEL0 DEL1 DEL2 DEL3 LATCHFF LATCH FF LSR RESET SET INDDMUX INDD LATCHFF D0 INFF INCK KEEPERMODE MILLIAMPS SIX TWELVE TWENTYFOUR NA OFF ON INPUT SIDE OFF ON
Figure 22. Series 4 PIO Image from ORCA Foundry Lucent Technologies Inc. 33
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
also be used to control the input latch/FF when it is configured as a FF instead of a latch, with the addition of another control signal used as a clock enable. The PIOs are paired together and have independent CE, set/reset, and GSRN control signals for the pair. Note that these control signals are paired to the same pair of pins used for differential signaling. The input path is also capable of accepting data from any pad using a fast capture feature. This feature can be programmed as a latch or FF referenced to any clock. There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system clock. To further improve setup time, the fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data from a dedicated latch that is clocked by a fast edge clock from the dedicated clock pads or any local pad. The input FF is then driven by a primary clock sourced from a dedicated input pin designed for fast, low-skew operation at the I/Os. These dedicated pads are located in pairs in the center of each side of the array and if not utilized by the clock spine can be used as general user I/O. The clock inputs to both the dedicated fast capture latch and the input FF can also be driven by the on-chip PLLs. The combination of input register capability provides for input signal demultiplexing without any additional resources such as for address and data arriving on the same pins. On the positive edge of the clock, the data would come from the pad to latch. The PIO input signal is sent to both the input latch and directly to INDD. The signal is latched on the falling edge of the clock and output to routing at INFF. The address and data are then both available at the rising edge of the clock. These signals may be registered or otherwise processed in the PLCs.
Programmable Input/Output Cells
(continued)
Inputs
There are many major options on the PIO inputs that can be selected in the ORCA Foundry tools listed in Table 15. Inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. A weak keeper circuit is also available on inputs. Input signals in a PIO are passed to CIB routing and/or a fast route into the clock routing system. There is also a programmable delay available on the input. When enabled, this delay affects the INFF and INDD signals of each PIO, but not the clock input. The delay allows any signal to have a guaranteed zero hold time when input. This feature is discussed subsequently. Inputs should have transition times of less than 500 ns and should not be left floating. If any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. Floating inputs increase power consumption, produce oscillations, and increase system noise. The inputs have a typical hysteresis of approximately 250 mV to reduce sensitivity to input noise. The PIC contains input circuitry that provides protection against latch-up and electrostatic discharge. The other features of the PIO inputs relate to the latch/ FF structure in the input path. In latch mode, the input signal is fed to a latch that is clocked by either the primary, secondary, or edge clock signal. The clock may be inverted or noninverted. There is also a local set/ reset signal to the latch. The senses of these signals are also programmable and have the capability to enable or disable the global set/reset signal and select the set/reset priority. The same control signals may
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is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the output buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. The PIO has both input and output shift register capabilities. This ability allows the data rate to be reduced from the pad or increased to the pad by two or four times. The shift register block (SRB) is available in groups of four PIO. Both the input and output shift registers are controlled by the same clock and can operate at the same time at the same speed as long as the SRB is not connected to the same pads.The output control signals are similar to the input control signals in that they are per pair of PIOs. Bus Hold Each PIO can be programmed with a KEEPERMODE feature. This element is user programmed for bus hold requirements. This mode retains the last known state of a bus when the bus goes into 3-state. It prevents floating buses and saves system power. PIO Register Control Signals The PIO latches/FFs have various clock, clock enable (CE), local set/reset (LSR), and GSRN controls. Table 16 provides a summary of these control signals and their effect on the PIO latches/FFs. Note that all control signals are optionally invertible. The output control signals are similar to the input control signals in that they are per pair of PIOs. Table 16. PIO Register Control Signals
Control Signal Edge Clock (ECLK) Effect/Functionality
Programmable Input/Output Cells
(continued) Table 15. PIO Options
Input Input Level Input Speed Float Value Register Mode Clock Sense Input Selection Keeper Mode LVDS Resistor Output Output Drive Current Output Function Output Speed Output Source Output Sense 3-State Sense FF Clocking Clock Sense Logic Options I/O Controls Clock Enable Option LVTTL, LVCMOS 2, LVCMOS 1.8, 3.3 V PCI Compliant. Fast, Delayed. Pull-up, Pull-down, None. Latch, FF, Fast Zero Hold FF, None (direct input). Inverted, Noninverted. Input 1, Input 2, Clock Input. On, Off. On, Off. Option 12 mA/6 mA or 6 mA/3 mA 24 mA/12 mA. Normal, Fast Open Drain. Fast, Slew. FF Direct-out, General Routing. Active-high, Active-low. Active-high, Active-low (3-state). Edge Clock, System Clock. Inverted, Noninverted. See Table 17. Option
Active-high, Active-low, Always Enabled. Set/Reset Level Active-high, Active-low, No Local Reset. Set/Reset Type Synchronous, Asynchronous. Set/Reset Priority CE over LSR, LSR over CE. GSR Control Enable GSR, Disable GSR.
Outputs The PIO's output drivers for TTL/CMOS outputs have programmable drive capability and slew rates. Two propagation delays (fast, slewlim) are available on output drivers. There are three combinations of programmable drive currents (24 mA sink/12 mA source, 12 mA sink/6 mA, and 6 mA sink/3 mA source). At powerup, the output drivers are in slewlim mode and 12 mA sink/6 mA source. If an output is not to be driven in the selected configuration mode, it is 3-stated. The output buffer signal can be inverted, and the 3-state control signal can be made active-high, activelow, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Additionally, there Lucent Technologies Inc.
Clocks input fast-capture latch; optionally clocks output FF, or 3-state FF. System Clock Clocks input latch/FF; optionally (SCLK) clocks output FF, or 3-state FF. Clock Enable Optionally enables/disables input FF (CE) (not available for input latch mode); optionally enables/disables output FF; separate CE inversion capability for input and output. Local Set/Reset Option to disable; affects input latch/ (LSR) FF, output FF, and 3-state FF if enabled. Global Set/Reset Option to enable or disable per PIO (GSRN) (the input FF, output FF, and 3-state FF) after initial configuration. Set/Reset Mode The input latch/FF, output FF, and 3-state FF are individually set or reset by both the LSR and GSRN inputs. 35
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Table 18. Compatible Mixed I/O Standards
VDDIO BANK Voltage 3.3 V 2.5 V 1.8 V 1.5 V Compatible Standards LVTTL, SSTL3-I, SSTL3-II, GTL, GTL+, PECL LVCMOS2, SSTL2-I, SSTL2-II, LVDS, LVPECL LVCMOS18 HSTL I, HSTL III, HSTL IV
Programmable Input/Output Cells
(continued) The PIO output FF can perform output data multiplexing with no PLC resources required. This type of scheme is necessary for DDR applications which require data clocking out of the I/O on both edges of the clock. In this scheme, the output of OUTFF and OUTDD are serialized and shifted out on both the positive and negative edges of the clock using the shift registers. The PIC logic block can also generate logic functions based on the signals on the OUTDD and CLK ports of the PIO. The functions are AND, NAND, OR, NOR, XOR, and XNOR. Table 17 is provided as a summary of the PIO logic options. Table 17. PIO Logic Options Option AND NAND OR NOR XOR XNOR Description Output logical AND of signals on OUTFF and clock. Output logical NAND of signals on OUTFF and clock. Output logical OR of signals on OUTFF and clock. Output logical NOR of signals on OUTFF and clock. Output logical XOR of signals on OUTFF and clock. Output logical XNOR of signals on OUTFF and clock.
TL
TC
TR
PLC ARRAY
BL
BC
BR
CR
CL
0205(F).
Figure 23. ORCA High-Speed I/O Banks High-Speed Memory Interfaces PIO features allow high-speed interfaces to external SRAM and/or DRAM devices. Series 4 I/Os provide 200 MHz ZBT requirements when switching between write and read cycles. ZBT allows 100% use of bus cycles during back-to-back read/write and write/read cycles. However, this maximum utilization of the bus increases probability of bus contention when the interfaced devices attempt to drive the bus to opposite logic values. The LVTTL I/O interfaces directly with commercial ZBT SRAMs signaling and allows the versatility to program the FPGA drive strengths from 6 mA to 24 mA. DDR allows data to be read or written on both the rising and the falling edge of the clock which delivers twice the bandwidth. QDR (quad data rate) are similar, but have separate read and write parts for over double the bandwidth. The DDR capability in the PIO also allows double the bandwidth per pin for generic transfer of data between two devices. DDR doubles the memory speed from SDRAMs without the need to increase clock frequency. The flexibility of the PIO allows 133 MHz/266 Mbits per second performance using the SSTL I/O features of the Series 4. All DDR interface functions are built into the PIO. Lucent Technologies Inc.
Flexible I/O features allow the user to select I/O to meet different high-speed interface requirements. These I/Os require different input references or supply voltages. The perimeter of the device is divided into groups of PIOs or buffer banks. For each bank, there is a separate VDDIO. Every device is equally broken up into eight I/O banks. The VDDIO supplies the correct output voltage for a particular standard. The user must supply the appropriate power supply to the VDDIO pin. Within a bank, several I/O standards may be mixed as long as they use a common VDDIO. Also, some interface standards require a specified threshold voltage known as VREF. In these modes, where a particular VREF is required, the device is automatically programmed to dedicate a pin for the appropriate VREF which must be supplied by the user. The VREF is dedicated exclusively to the bank and cannot be intermixed with other signaling requiring other VREF voltages. However, pins not requiring VREF can be mixed in the bank. The VREF pad is then no longer available to the user for general use. See Table 14 for a list of the I/O standards supported. 36
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells (continued)
LVDS I/O The LVDS differential pair I/O standard allows for high-speed, low-voltage swing and low-power interfaces defined by industry standards: ANSI*/TIA/EIA-644 and IEEE 1596.3 SSI-LVDS. The general-purpose standard is supplied without the need for an input reference supply and uses a low switching voltage which translates to low ac power dissipation. The ORCA LVDS I/O provides an integrated 100 matching resistor used to provide a differential voltage across the inputs of the receiver. The on-chip integration provides termination of the LVDS receiver without the need of discrete external board resistors. The user has the programmable option to enable termination per receiver pair for point-to-point applications or, in multipoint interfaces, limit the use of termination to bused pairs. If the user chooses to terminate any differential receiver, a single LVDS_R pin is dedicated to connect a single 100 resistor to VSS, which will provide a balance termination to all of the LVDS receiver pairs programmed to termination. See Table 20 for the LVDS termination pin location. Table 19 provides the dc specifications for the ORCA LVDS solution. Table 19. LVDS I/O Specifications
Parameter Built-in Receiver Differential Input Resistor Receiver Input Voltage Differential Input Threshold Output Common-mode Voltage Input Common-mode Voltage Min 95 0.0 -100 1.125 0.2 Typical 100 -- -- 1.25 1.25 Max 105 2.4 100 1.375 2.2 Unit V mV V V
Table 20. LVDS Termination Pin Dedicated Chip LVDS External Termination Pin (LVDS_R) Per Package BA352 AC3 PIO Downlink/Uplink Each group of four PIO have access to an input/output shift register as shown in Figure 24. This feature allows highspeed input data to be divided down by 1/2 or 1/4, and output data can be multiplied by 2x or 4x its internal speed. Both the input and output shift can be programmed to operate at the same time. However, the same PIO cannot be used for both input and output shift registers at the same time. For input shift mode, the data from INDD from the PIO is connected to the input shift register. The input data is divided down and is returned to the routing through the INSH nodes. In 4x mode, all the INSH nodes are used. 2x mode uses INSH4 and INSH3. Similarly, the output shift register brings data into the register from dedicated OUTSH nodes. 4x mode uses all the OUTSH signals. However, only OUTSH2 and OUTSH1 are used for 2x mode. BC432 AH29 BM680 AL1
* ANSI is a registered trademark of American National Standards Institute, Inc. EIA is a registered trademark of Electronic Industries Association.
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Programmable Input/Output Cells (continued)
PIO
PIO
PIO
PIO
OUTDD
OUTDD
OUTDD
OUTDD
OUTSH
OUTSH
OUTSH
OUTSH
INDD
INDD
INDD
INDD
SHIFT REGISTER INTO FPGA
SHIFT REGISTER OUT FROM FPGA CLK
INTSH2
INSH4
INSH3
INSH1
OUTSH4
OUTSH2
OUTSH3
OUTSH1
0204(F).
Figure 24. PIO Shift Register
Special Function Blocks
Internal Oscillator The internal oscillator resides in the upper left corner of the FPGA array. It has output clock frequencies of 1.25 MHz and 10 MHz. The internal oscillator is the source of the internal CCLK used for configuration. It may also be used after configuration as a generalpurpose clock signal. Global Set/Reset (GSRN) The GSRN logic resides in the lower-right corner of the FPGA. GSRN is an invertible (default active-low) signal that is used to reset all of the user-accessible latches/ FFs on the device. GSRN is automatically asserted at powerup and during configuration of the device. The timing of the release of GSRN at the end of configuration can be programmed in the start-up logic described below. Following configuration, GSRN may be connected to the RESET pin via dedicated routing, or it may be connected to any signal via normal routing. Within each PFU and PIO, individual FFs and latches 38
can be programmed to either be set or reset when GSRN is asserted. Series 4 allows individual PFUs and PIOs to turn off the GSRN signal to its latches/FFs after configuration. The RESET input pad has a special relationship to GSRN. During configuration, the RESET input pad always initiates a configuration abort, as described in the FPGA States of Operation section. After configuration, the GSRN can either be disabled (the default), directly connected to the RESET input pad, or sourced by a lower-right corner signal. If the RESET input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. Start-Up Logic The start-up logic block can be configured to coordinate the relative timing of the release of GSRN, the activation of all user I/Os, and the assertion of the DONE signal at the end of configuration. If a start-up clock is used to time these events, the start-up clock can come from CCLK, or it can be routed into the startup block using lower-right corner routing resources.
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Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
between BSCAN devices (U2 and U3), and out TDO of the last BSCAN device (U4). In this configuration, the TMS and TCK signals are routed to all boundary-scan ICs in parallel so that all boundary-scan components operate in the same state. In other configurations, multiple scan paths are used instead of a single ring. When multiple scan paths are used, each ring is independently controlled by its own TMS and TCK signals. Figure 26 provides a system interface for components used in the boundary-scan testing of PCBs. The three major components shown are the test host, boundaryscan support circuit, and the devices under test (DUTs). The DUTs shown here are ORCA Series FPGAs with dedicated boundary-scan circuitry. The test host is normally one of the following: automatic test equipment (ATE), a workstation, a PC, or a microprocessor.
S TMS TDI TCK TDO TMS TDI TCK TDO U2
Special Function Blocks (continued)
Temperature Sensing The built-in temperature-sensing diodes allow junction temperature to be measured during device operation. A physical pin (PTEMP) is dedicated for monitoring device junction temperature. PTEMP works by forcing a 10 A current in the forward direction, and then measuring the resulting voltage. The voltage decreases with increasing temperature at approximately -1.69 mV/C. A typical device with a 85 C device temperature will measure approximately 630 mV. Table 21. Dedicated Temperature Sensing Dedicated Temperature Sensing Diode Pin Per Package BA352 AB3 Boundary-Scan The IEEE standards 1149.1 and 1149.2 (IEEE Standard test access port and boundary-scan architecture) are implemented in the ORCA series of FPGAs. It allows users to efficiently test the interconnection between integrated circuits on a PCB as well as test the integrated circuit itself. The IEEE 1149 standard is a well-defined protocol that ensures interoperability among boundary-scan (BSCAN) equipped devices from different vendors. Series 4 FPGAs are also compliant to IEEE standard 1532/D1. This standard for boundary-scan based insystem configuration of programmable devices provides a standardized programming access and methodology for FPGAs. A device, or set of devices, implementing this standard may be programmed, read back, erased verified, singly or concurrently, with a standard set of resources. The IEEE 1149 standards define a test access port (TAP) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of integrated circuits in a system. The ORCA Series FPGA provides four interface pins: test data in (TDI), test mode select (TMS), test clock (TCK), and test data out (TDO). The PRGM pin used to reconfigure the device also resets the boundary-scan logic. The user test host serially loads test commands and test data into the FPGA through these pins to drive outputs and examine inputs. In the configuration shown in Figure 26, where boundary-scan is used to test ICs, test data is transmitted serially into TDI of the first BSCAN device (U1), through TDO/TDI connections Lucent Technologies Inc. BC432 AH31 BM680 AK4
net a
U1
net b net c
TDI TMS TCK TDO TMS TDI TCK TDO U3 TMS TDI TCK TDO U4
SEE ENLARGED VIEW BELOW. TDO TCK TMS TDI PT[ij] TAPC BYPASS REGISTER INSTRUCTION REGISTER SCAN OUT BSC BDC p_in p_out SCAN IN PR[ij] DCC p_ts
SCAN IN
SCAN OUT
BSC DCC BDC PL[ij]
p_ts p_out p_in PLC ARRAY
p_in p_out p_ts
BSC BDC DCC
SCAN IN p_ts SCAN OUT
p_out p_in SCAN IN
SCAN OUT
BSC DCC BDC
PB[ij]
5-5972(F)
Key: BSC = boundary-scan cell, BDC = bidirectional data cell, and DCC = data control cell.
Figure 25. Printed-Circuit Board with BoundaryScan Circuitry 39
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Special Function Blocks (continued)
D[7:0] D[7:0] LUCENT BOUNDARYSCAN MASTER MICROPROCESSOR CE RA R/W DAV INT SP TMS0 TCK (BSM) TDI TDO TDI ORCA SERIES FPGA TMS (DUT) TCK TDO TDI ORCA SERIES FPGA TMS (DUT) TCK TDO
INTR
TDI ORCA SERIES FPGA TMS (DUT) TCK
TDO
5-6765(F)
Figure 26. Boundary-Scan Interface
The boundary-scan support circuit shown in Figure 26 is the 497Aa boundary-scan master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general MPI and provides parallel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PC-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Boundary-Scan Instructions The Series 4 boundary-scan circuitry includes ten IEEE 1149.1, 1149.2, and 1532/D1 instructions and six ORCA-defined instructions. These also include one IEEE 1149.3 optional instruction. A 6-bit wide instruction register supports all the instructions listed in Table 22. The BYPASS instruction passes data internally from TDI to TDO after being clocked by TCK.
Table 22. Boundary-Scan Instructions Code 000000 000001 000011 000100 000101 000110 001000 001001 001010 001011 001101 001110 010001 010010 010011 010100 010101 111111 Instruction EXTEST SAMPLE PRELOAD RUNBIST IDCODE USERCODE ISC_ENABLE ISC_PROGRAM ISC_NOOP ISC_DISABLE ISC_PROGRAM_USERCODE ISC_READ PLC_SCAN_RING1 PLC_SCAN_RING2 PLC_SCAN_RING3 RAM_WRITE RAM_READ BYPASS
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RAMs, ROMs, FIFOs, etc., and the surrounding RANDOM logic in the circuit. Also implemented in Series 4 devices is the IEEE 1532/D1 standards for in-system configuration for programmable logic devices. Included are four mandatory and two optional instructions defined in the standards. ISC_ENABLE, ISC_PROGRAM, ISC_NOOP and , ISC_DISABLE are the four mandatory instructions. ISC_ENABLE initializes the devices for all subsequent ISC instructions. The ISC_PROGRAM instruction is similar to the RAM_WRITE instruction implemented in all ORCA devices where the user must monitor the PINITN pin for a high indicating the end of initialization and a successful configuration can be started. The ISC_PROGRAM instruction is used to program the configuration memory through a dedicated ISC_Pdata register. The ISC_NOOP instruction is used when programming multiple devices in parallel. During this mode, TDI and TDO behave like BYPASS. The data shifted through TDI is shifted out through TDO. However, the output pins remain in control of the BSR, unlike BYPASS where they are driven by the system logic. The ISC_DISABLE is used upon completion of the ISC programming. No new ISC instructions will be operable without another ISC_ENABLE instruction. Optional 1532/D1 instructions include ISC_PROGRAM_USERCODE. When this instruction is loaded, the user shifts all 32 bits of a user-defined ID (LSB first) through TDI. This overwrites any ID previously loaded into the ID register. This ID can then be read back through the USERCODE instruction defined in IEEE 1149.2. ISC_READ is similar to the ORCA RAM_Read instruction which allows the user to read back the configuration RAM contents serially out on TDO. Both must monitor the PDONE signal to determine weather or not configuration is completed. ISC_READ used a 1-bit register to synchronously read back data coming from the configuration memory. The readback data is clocked into the ISC_READ data register and then clocked out TDO on the falling edge or TCK.
Special Function Blocks (continued)
The external test (EXTEST) instruction allows the interconnections between ICs in a system to be tested for opens and stuck-at faults. If an EXTEST instruction is performed for the system shown in Figure 25, the connections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether this same value is seen at the other device. This is determined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the BSR until each one aligns to the appropriate pin. Then, based upon the value of the 3-state signal, either the I/O pad is driven to the value given in the BSR, or the BSR is updated with the input value from the I/O pad, which allows it to be shifted out TDO. The SAMPLE and PRELOAD instructions are useful for system debugging and fault diagnosis by allowing the data at the FPGA's I/Os to be observed during normal operation or written during test operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PIOs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3-state control signal. For preload operation, data is written from the BSR to all of the I/Os simultaneously. There are six ORCA-defined instructions. The PLC scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow userdefined internal scan paths using the PLC latches/FFs and routing interface. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 23. An optional IEEE 1149.3 instruction RUNBIST has been implemented. This instruction is used to invoke the built-in self-test (BIST) of regular structures like Table 23. Series 4E Boundary-Scan Vendor-ID Codes Device OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Version (4-bit) 0000 0000 0000 0000 0000 Part* (10-bit) 0011100000 0001010000 0000110000 0011110000 0010001000
Family (6-bit) 001000 001000 001000 001000 001000
Manufacturer (11-bit) 00000011101 00000011101 00000011101 00000011101 00000011101
LSB (1-bit) 1 1 1 1 1
* PLC array size of FPGA, reverse bit order. Note: Table assumes version 0.
Lucent Technologies Inc.
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The bypass instruction uses a single FF, which resynchronizes test data that is not part of the current scan operation. In a bypass instruction, test data received on TDI is shifted out of the bypass register to TDO. Since the BSR (which requires a two FF delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. The boundary-scan logic is enabled before and during configuration. After configuration, a configuration option determines whether or not boundary-scan logic is used. The 32-bit boundary-scan identification register contains the manufacturer's ID number, unique part number, and version (as described earlier). The identification register is the default source for data on TDO after RESET if the TAP controller selects the shiftdata-register (SHIFT-DR) instruction. If boundary scan is not used, TMS, TDI, and TCK become user I/Os, and TDO is 3-stated or used in the readback operation. An optional USERCODE is available. The USERCODE is a 32-bit value that the user can set during device configuration and can be written to and read from the FPGA via the boundary-scan logic.
Special Function Blocks (continued)
ORCA Boundary-Scan Circuitry The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass register. It also includes circuitry to support the 18 predefined instructions. Figure 27 shows a functional diagram of the boundaryscan circuitry that is implemented in the ORCA Series. The input pins' (TMS, TCK, and TDI) locations vary depending on the part, and the output pin is the dedicated TDO/RD_DATA output pad. Test data in (TDI) is the serial input data. Test mode select (TMS) controls the boundary-scan TAPC. Test clock (TCK) is the test clock on the board. The BSR is a series connection of boundary-scan cells (BSCs) around the periphery of the IC. Each I/O pad on the FPGA, except for CCLK, DONE, and the boundaryscan pins (TCK, TDI, TMS, and TDO), is included in the BSR. The first BSC in the BSR (connected to TDI) is located in the first PIO I/O pad on the left of the top side of the FPGA (PTA PIO). The BSR proceeds clockwise around the top, right, bottom, and left sides of the array. The last BSC in the BSR (connected to TDO) is located on the top of the left side of the array (PL1D).
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Special Function Blocks (continued)
I/O BUFFERS DATA REGISTERS BOUNDARY-SCAN REGISTER IDCODE REGISTER PSR1/PSR2/PSR3 REGISTERS (PLCs) USER CODE REGISTERS VDD CONFIGURATION REGISTER (RAM_R, RAM_W) BYPASS REGISTER DATA MUX
TDI
INSTRUCTION DECODER M U X TDO
VDD
RESET CLOCK DR SHIFT-DR UPDATE-DR
INSTRUCTION REGISTER RESET CLOCK IR SHIFT-IR UPDATE-IR
TMS VDD TCK VDD PRGM TAP CONTROLLER
SELECT ENABLE PUR
5-5768(F)
Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram ORCA Series TAP Controller The ORCA Series TAP controller is a 1149 compatible TAPC. The 16 JTAG state assignments from the IEEE 1149 specification are used. The TAPC is controlled by TCK and TMS. The TAPC states are used for loading the IR to allow three basic functions in testing: providing test stimuli (Update-DR), providing test execution (Run-Test/Idle), and obtaining test responses (CaptureDR). The TAPC allows the test host to shift in and out both instructions and test data/results. The inputs and outputs of the TAPC are provided in the table below. The outputs are primarily the control signals to the instruction register and the data register. Table 24. TAP Controller Input/Outputs Symbol TMS TCK PUR
PRGM
I/O I I I I O O O O O O O O O
Function Test Mode Select Test Clock Powerup Reset BSCAN Reset Test Logic Reset Select IR (High); Select-DR (Low) Test Data Out Enable Capture/Parallel Load-DR Capture/Parallel Load-IR Shift Data Register Shift Instruction Register Update/Parallel Load-DR Update/Parallel Load-IR
TRESET Select Enable Capture-DR Capture-IR Shift-DR Shift-IR Update-DR Update-IR
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Special Function Blocks (continued)
The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This sequences the TAPC through states in order to perform the desired function on the instruction register or a data register. Figure 28 provides a diagram of the state transitions for the TAPC. The next state is determined by the TMS input value.
1
TEST-LOGICRESET 0 RUN-TEST/ IDLE 1 SELECTDR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECTIR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
0
5-5370(F)
Figure 28. TAP Controller State Transition Diagram Boundary-Scan Cells Figure 29 is a diagram of the boundary-scan cell (BSC) in the ORCA series PIOs. There are four BSCs in each PIO: one for each pad, except as noted above. The BSCs are connected serially to form the BSR. The BSC controls the functionality of the in, out, and 3-state signals for each pad. The BSC allows the I/O to function in either the normal or test mode. Normal mode is defined as when an output buffer receives input from the PLC array and provides output at the pad or when an input buffer provides input from the pad to the PLC array. In the test mode, the BSC executes a boundary-scan operation, such as shifting in scan data from an upstream BSC in the BSR, providing test stimuli to the pad, capturing test data at the pad, etc. The primary functions of the BSC are shifting scan data serially in the BSR and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. The BSC consists of two circuits: the bidirectional data cell is used to access the input and output data, and the direction control cell is used to access the 3-state value. Both cells consist of a FF used to shift scan data which feeds a FF to control the I/O buffer. The bidirectional data cell is connected serially to the direction control cell to form a boundary-scan shift register. The TAPC signals (capture, update, shiftn, treset, and TCK) and the MODE signal control the operation of the BSC. The bidirectional data cell is also controlled by the high out/low in (HOLI) signal generated by the direction control cell. When HOLI is low, the bidirectional data cell receives input buffer data into the BSC. When HOLI is high, the BSC is loaded with functional data from the PLC.
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Special Function Blocks (continued)
The MODE signal is generated from the decode of the instruction register. When the MODE signal is high (EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE), functional data from the FPGA's internal logic is propagated to the output buffer. The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the ORCA Foundry CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information.
SCAN IN I/O BUFFER PAD_IN p_in BIDIRECTIONAL DATA CELL PAD_OUT
0 0 0 1 D Q D Q 1
PAD_TS
p_out
1
HOLI
0 0
p_ts
D
Q
D
Q
1
1
DIRECTION CONTROL CELL
SHIFTN/CAPTURE
TCK
SCAN OUT UPDATE/TCK
MODE
5-2844(F)
Figure 29. Boundary-Scan Cell Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum frequency allowed for TCK is 10 MHz. Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is clocked into the DUT on the rising edge.
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Special Function Blocks (continued)
TEST-LOGIC-RESET SELECT-DR-SCAN SELECT-IR-SCAN RUN-TEST/IDLE RUN-TEST/IDLE
CAPTURE-IR
PAUSE-IR
TCK
TMS
TDI
EXIT1-IR
UPDATE-IR
SHIFT-IR
EXIT1-IR
EXIT2-IR
SHIFT-IR
5-5971(F)
Figure 30. Instruction Register Scan Timing Diagram
Readback Logic The readback logic can be enabled via a bit stream option or by instantiation of a library readback component. Readback is used to read back the configuration data and, optionally, the state of all PFU and PIO FF outputs. A readback operation can be done while the FPGA is in normal system operation. The readback operation can be daisy-chained. To use readback, the user selects options in the bit stream generator in the ORCA Foundry development system. Table 25 provides readback options selected in the bit stream generator tool. The table provides the number of times that the configuration data can be read back. This is intended primarily to give the user control over the security of the FPGA's configuration program. The user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (U). Table 25. Readback Options Option 0 1 U Function Prohibit Readback Allow One Readback Only Allow Unrestricted Number of Readbacks
Readback can be performed via the Series 4 MPI or by using dedicated FPGA readback controls. If the MPI is enabled, readback via the dedicated FPGA readback logic is disabled. Readback using the MPI is discussed in the MPI section. The pins used for dedicated readback are readback data (RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is initiated by a high-to-low transition on RD_CFG. The RD_CFG input must remain low during the readback operation. The readback operation can be restarted at frame 0 by driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low again. One bit of data is shifted out on RD_DATA at the rising edge of CCLK. The first start bit of the readback frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see the readback timing characteristics table in the timing characteristics section). To be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair.
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The readback frame has an identical format to that of the configuration data frame, which is discussed later in the Configuration Data Format section. If LUT memory is not used as RAM and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. This eases a bitwise comparison between the configuration and readback data. The configuration header, including the length count field, is not part of the readback frame. The readback frame contains bits in locations not used in the configuration. These locations need to be masked out when comparing the configuration and readback frames. The development system optionally provides a readback bit stream to compare to readback data from the FPGA. Also note that if any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as the original configuration data frame either. Global 3-State Control (TS_ALL) To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. The TS_ALL signal is driven from either an external pin or an internal signal. Before and during configuration, the TS_ALL signal is driven by the input pad RD_CFG. After configuration, the TS_ALL signal can be disabled, driven from the RD_CFG input pad, or driven by a general routing signal in the upper right corner. Before configuration, TS_ALL is active-low; after configuration, the sense of TS_ALL can be inverted. The following occur when TS_ALL is activated:
s s s
Special Function Blocks (continued)
Readback can be initiated at an address other than frame 0 via the new MPI control registers (see the Microprocessor Interface section for more information). In all cases, readback is performed at sequential addresses from the start address. It should be noted that the RD_DATA output pin is also used as the dedicated boundary-scan output pin, TDO. If this pin is being used as TDO, the RD_DATA output from readback can be routed internally to any other pin desired. The RD_CFG input pin is also used to control the global 3-state (TS_ALL) function. Before and during configuration, the TS_ALL signal is always driven by the RD_CFG input and readback is disabled. After configuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. If used as the RD_CFG input for readback, the internal TS_ALL input can be routed internally to be driven by any input pin. The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIO outputs can be captured. The following options are allowed when doing a capture of the PFU outputs:
s
Do not capture data (the data written to the RAMs, usually 0, will be read back). Capture data upon entering readback. Capture data based upon a configurable signal internal to the FPGA. If this signal is tied to logic 0, capture RAMs are written continuously. Capture data on either options two or three above.
s s
All of the user I/O output buffers are 3-stated. The TDO/RD_DATA output buffer is 3-stated. The RD_CFG, RESET, and PRGM input buffers remain active with a pull-up. The DONE output buffer is 3-stated, and the input buffer is pulled up.
s
s
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Microprocessor Interface (MPI)
The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC MPC860/MPC8260 series microprocessors. The pin listing is shown in Table 26. The MPI implements an 8-, 16-, or 32-bit interface with 4-bit parity to the host processor (PowerPC) that can be used for configuration and readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In addition to dedicated-function registers, the MPI bridges to the AMBA embedded system bus through which the PowerPC bus master can access the FPGA configuration logic, EBR, and other user logic. There is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the embedded system bus. The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4- bit. In configuration mode, the data bus width and parity are related to the state of the M[0:3] mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ORCA macro library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the configuration bit stream. These pads can be used as general I/O when they are not needed for MPI use. The ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The MPI interfaces to the user-programmable FPGA logic using the AMBA embedded system bus. The MPI has access to a series of addressable registers made accessible by the AMBA system bus that provide FPGA control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The address map for these registers and the user-logic address space utilize the same registers as the AMBA embedded system bus. The internal AMBA bus is 32 bits wide and the proper transformation of 8-, 16-, or 32-bit data of the MPI is done when transferring data between the MPI and ESB. Table 26. MPC 860 to ORCA MPI Interconnection PowerPC Signal D[n:0] DP[m:0] A[14:31] TS BURST -- -- CLKOUT RD/WR TA BDIP ORCA Pin Name D[31:0] DP[3:0] A[17:0] MPI_STRB MPI_BURST CS0 CS1 MPI_CLK MPI_RW MPI_ACK MPI_BDIP MPI I/O I/O I/O I I I I I I I O O 8-, 16-, 32-bit data bus. Selectable parity bus width from 1-, 2-, and 4-bit. 32-bit MPI address bus. Transfer start signal. Active-low indicates burst transfer in-progress/high indicates current transfer not a burst. Active-low MPI select. Active-high MPI select. PowerPC interface clock. Read (high)/write (low) signal. Active-low transfer acknowledge signal. Active-low burst transfer in progress signal indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. Active-low interrupt request signal. Active-low indicates MPI detects a bus error on the internal system bus for current transaction. Requests the MPC860 to relinquish the bus and retry the cycle. Function
Any of IRQ[7:0] TEA RETRY
MPI_IRQ MPI_TEA MPI_RTRY
O O O
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A single bus arbiter controls the traffic on the bus by ensuring that only one master has access to the bus at any time. The arbiter monitors a number of different requests to use the bus and decides which request is currently the highest priority. The configuration modes have the highest priority and overrides all normal user modes. Priority can be programmed between MPI and user logic at configuration in generic FPGAs. If no priority is set, a round-robin approach is used by granting the next requesting master in a rotating fixed order. Several interfaces exist between the ESB and other FPGA elements. The MPI interface acts as a bridge between the external microprocessor bus and ESB. The MPI may have different clock domains than the ESB if the ESB clock is not sourced from the external microprocessor clock. Pipelined operation allows highspeed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of the nature of the transfers. Table 27 is a listing of the ESB register file and brief descriptions. Table 28 shows the system interrupt registers, and Table 29 and Table 30 show the FPGA status and command registers, all with brief descriptions.
Embedded System Bus (ESB)
Implemented using the open standard, on-chip bus AMBA-AHB 2.0 specification, the Series 4 devices connects all the FPGA elements together with a standardized bus framework. The ESB facilitates communication among MPI, configuration, EBRs, and user logic in all the generic FPGA devices. AHB serves the need for high-performance SoC as well as aligning with current synthesis design flows. Multiple bus masters optimize system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32 bits with 4-bit parity supports the high-bandwidth of data-intensive applications of using the wide on-chip memory. AMBA enhances a reusable design methodology by defining a common backbone for IP modules. The ESB is a synchronous bus that is driven by either the MPI clock, internal oscillator, CCLK (slave configuration modes), TCK (JTAG configuration modes), or by a user clock from routing. During initial configuration and reconfiguration, the bus clock is defaulted to the configuration clock. The postconfiguration clock source is set during configuration. The user has the ability to program several slaves through the user logic interface. Embedded block RAM also interfaces seamlessly to the AHB bus.
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Embedded System Bus (ESB) (continued)
Table 27. Embedded System Bus/MPI Registers Register 00 01 02 03 04 Byte 03--00 07--04 0B--08 0F--0C 13 12 11 10 17--14 1B--18 1F--1C 23--20 27--24 2B--28 2F--2C 33--30 37--34 3B--38 3F--3C 43--40 47--44 53--50 63--60 67--64 73--70 Read/Write Initial Value RO R/W R/W RO R/W R/W R/W RO R/W RO R/W RO RO RO RO RO RO RO RO -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description 32-bit device ID Scratchpad register Command register Status register Interrupt enable register--MPI Interrupt enable register--USER Interrupt enable register--FPSC Interrupt cause register Readback address register (14 bits) Readback data register Configuration data register Reserved Bus error address register Interrupt vector 1 predefined by configuration bit stream Interrupt vector 2 predefined by configuration bit stream Interrupt vector 3 predefined by configuration bit stream Interrupt vector 4 predefined by configuration bit stream Interrupt vector 5 predefined by configuration bit stream Interrupt vector 6 predefined by configuration bit stream Top-left PPLL control/status Top-left HPLL control/status Top-right PPLL control/status Bottom-left PPLL control/status Bottom-left HPLL control/status Bottom-right PPLL control/status
05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 14 18 19 1C
Table 28. Interrupt Register Space Assignments Byte 13 12 11 10 Bit 7--0 7--0 7--0 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W RO RO RO RO RO RO RO RO Description
Interrupt enable register--MPI Interrupt enable register--USER Interrupt enable register--FPSC Interrupt cause registers USER_IRQ_GENERAL; USER_IRQ_SLAVE; USER_IRQ_MASTER; CFG_IRQ_DATA; ERR_FLAG 1 MPI_IRQ FPSC_IRQ_SLAVE; FPSC_IRQ_MASTER
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Embedded System Bus (ESB) (continued)
Table 29. Status Register Space Assignments Byte 0F 0E OD Bit 7:0 7:0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Read/Write -- -- RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Description Reserved Reserved Configuration write data acknowledge Readback data ready Unassigned (zero) Unassigned (zero) FPSC_BIT_ERR RAM_BIT_ERR Configuration write data size (1, 2, or 4 bytes) Use with above for HSIZE[1:0] (byte, half-word, word) Readback addresses out of range Error response received by CFG from system bus Error responses received by CFG from system bus Unassigned (zero) Unassigned (zero) Unassigned (zero) ERR_FLAG 1 ERR_FLAG 0
0C
Table 30. Command Register Space Assignments Byte 08 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7:0 7:0 Description Bus reset from MPI > drives HRESETn Bus reset from USER > drives HRESETn Bus reset from FPSC > drives HRESETn SYS_DAISY REPEAT_RDBK (Don't increment readback address.) MPI_USR_ENABLE Readback data size (1, 2, or 4 bytes) Use with above for HSIZE[1:0] R/W SYS_GSR (GSR Input) SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active-high) PRGM from MPI > (similar to FPGA pin, but active-high) PRGM from USER > (similar to FPGA pin, but active-high) PRGM from FPSC > (similar to FPGA pin, but active-high) LOCK from MPI LOCK from USER LOCK from FPSC Reserved Reserved
09
0A 0B
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The PPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs across the entire device. The PPLLs can drive onto the primary, secondary, and edge clock networks inside the FPGA. Each PPLL can take a clock input from the dedicated pad or differential pair of pads in its corner or from general routing resources. Functionality of the PPLLs is programmed during operation through a read/write interface to the internal system bus command and status registers or via the configuration bit stream. There is also a PLL output signal, LOCK, that indicates a stable output clock state. Unlike Series 3, this signal does not have to be intergrated before use.
Phase-Locked Loops
There are eight PLLs available to perform many clock modification and clock conditioning functions on the Series 4 FPGAs. Six of the PLLs are programmable allowing the user the flexibility to configure the PLL to manipulate the frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs are capable of manipulating and conditioning clocks from 20 MHz to 200 MHz and two others are capable of manipulating and conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors with the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs (MCLK, NCLK) that can have programmable (12.5% steps) phase differences. Table 31. PPLL Specifications Parameter VDD1.5 VDD3.3 Operating Temp Input Clock Voltage Output Clock Voltage Input Clock Frequency (no division) Output Clock Frequency Min
Nom
Max
Unit V V C V V MHz MHz % % mW mA pA UIp-p s -- -- % % degree
PPLL HPPLL PPLL HPPLL
Input Duty Cycle Tolerance Output Duty Cycle dc Power Total On Current Total Off Current Cycle to Cycle Jitter (p-p) Lock Time Frequency Multiplication Frequency Division Duty Cycle Adjust of Output Clock Delay Adjust of Output Clock Phase Shift Between MCLK & NCLK
1.425 1.5 1.575 3.0 3.3 3.6 -40 25 125 1.425 1.5 1.575 1.425 1.5 1.575 20 -- 200 60 -- 420 20 -- 200 60 -- 420 30 -- 70 45 50 55 -- 28 -- -- 8.5 -- -- 30 -- -- <0.02 -- -- <50 -- 1x, 2x, 3x, 4x, 5x, 6x, 7x, 8x, 1/8, 1/7, 1/6, 1/5, 1/4, 1/3, 1/2 12.5, 25, 37.5, 50, 62.5, 75, 87.5 0, 12.5, 25, 37.5, 50, 62.5, 75, 87.5 0, 45, 90, 135, 180, 225, 270, 315
Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target very tightly specified clock conditioning not available in the universal PPLLs. DPLLs are targeted to low-speed networking DS1 and E1 and high-speed SONET/SDH networking STS-3 and STM-1 systems.
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Phase-Locked Loops (continued)
Table 32. DPLL DS-1/E-1 Specifications Parameter VDD1.5 VDD3.3 Operating Temp Input Clock Voltage Output Clock Voltage Input Clock Frequency Output Clock Frequency Input Duty Cycle Tolerance Output Duty Cycle dc Power Total On Current Total Off Current Cycle to Cycle Jitter (p-p) Lock Time Min 1.425 3.0 -40 1.425 1.425 1.0 -- -- 30 47 -- -- -- Nom 1.5 3.3 25 1.5 1.5 -- 1.544 2.048 -- 50 20 2.5 40 0.015 at 1.544 MHz 0.05 at 2.048 MHz <1200 Max 1.575 3.6 125 1.575 1.575 2.5 -- -- 70 53 -- -- -- Unit V V C V V MHz MHz % % mW mA pA UIp-p s
--
--
A dedicated pin PLL_VF is needed for externally connecting a low-pass filter circuit, as shown in Table 33. This provides the specified DS-1/E-1 PLL operating condition.
C1 R C2 R = 6 k WITH 1% ACCURACY C1 = 100 pF 5% ACCURACY C2 = 0.01 F 5% ACCURACY DEDICATED VSS PLL1
PLL_VF HPPLL
LPPLL
LPPLL
LPPLL
LPPLL
HPPLL
PLL2
1001(F).
Figure 31. PLL_VF External Requirements
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Phase-Locked Loops (continued)
Table 33. Dedicated Pin Per Package Dedicated PLL_VF Pin Per Package BA352 B24 BC432 C4 BM680 D30
Table 34. STS-3/STM-1 DPLL Specifications Parameter Input Clock Frequency Output Clock Frequency Input Duty Cycle Tolerance Output Duty Cycle dc Power Total On Current Total Off Current Cycle to Cycle Jitter (p-p) Lock Time Min -- -- 30 47 -- -- -- -- Nom 155.52 155.52 -- 50 50 2.4 30 0.02 <50 Max -- -- 70 53 -- -- -- -- Unit MHz MHz % % mW mA pA UIp-p s
ULPPLL ULHPPLL
URPPLL URPLL1
LLPPLL LLHPPLL
LRPPLL LRPLL2
0045(F)
Figure 32. PLL Naming Scheme
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Phase-Locked Loops (continued)
Table 35. Phase-Lock Loops Index Name [UL][LL][UR][LR]PPLL [UL][LL]HPPLL URPLL1 LRPLL2 Description Universal user-programmable PLL (20 MHz--200 MHz) Universal user-programmable PLL (60 MHz--420 MHz) DS-1/E-1 dedicated PLL STS-1/STM-1 dedicated PLL
FPGA States of Operation
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration, and start-up. Figure 33 outlines these three states.
POWERUP - POWER-ON TIME DELAY
INITIALIZATION - CLEAR CONFIGURATION MEMORY - INIT LOW, HDC HIGH, LDC LOW
YES
BIT ERROR
RESET, INIT, OR PRGM LOW NO
YES
NO
CONFIGURATION - M[3:0] MODE IS SELECTED - CONFIGURATION DATA FRAME WRITTEN - INIT HIGH, HDC HIGH, LDC LOW - DOUT ACTIVE
RESET OR PRGM LOW
START-UP - ACTIVE I/O - RELEASE INTERNAL RESET - DONE GOES HIGH PRGM LOW
OPERATION
5-4529(F).
Figure 33. FPGA States of Operation
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initialization state is extended to ensure that, in daisychain operation, all daisy-chained slave devices are ready. Independent of differences in clock rates, master mode devices remain in the initialization state an additional six internal clock cycles after INIT goes high. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count configuration clock cycles applied to the FPGA. As each configuration data frame is supplied to the FPGA, it is internally assembled into data words. Each data word is loaded into the internal configuration memory. The configuration loading process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. During configuration, the PIO and PLC latches/FFs are held set/reset and the internal BIDI buffers are 3-stated. The combinatorial logic begins to function as the FPGA is configured. Figure 34 shows the general waveform of the initialization, configuration, and startup states.
FPGA States of Operation (continued)
Initialization
Upon powerup, the device goes through an initialization process. First, an internal power-on-reset circuit is triggered when power is applied. Dedicated power pins called VDD33 are used by the configuration logic. When VDD33 reaches the voltage at which portions of the FPGA begin to operate (2.0 V), the I/Os are configured based on the configuration mode, as determined by the mode select inputs M[2:0]. A time-out delay is initiated when VDD33 reaches between 2.7 V to 3.0 V to allow the power supply voltage to stabilize. The INIT and DONE outputs are low. At powerup, if VDD33 does not rise from 2.0 V to VDD33 in less than 25 ms, the user should delay configuration by inputting a low into INIT, PRGM, or RESET until VDD33 is greater than the recommended minimum operating voltage. At the end of initialization, the default configuration option is that the configuration RAM is written to a low state. This prevents shorts prior to configuration. As a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration RAM first. The active-low, open-drain initialization signal INIT is released and must be pulled high by an external resistor when initialization is complete. To synchronize the configuration of multiple FPGAs, one or more INIT pins should be wire-ANDed. If INIT is held low by one or more FPGAs or an external device, the FPGA remains in the initialization state. INIT can be used to signal that the FPGAs are not yet initialized. After INIT goes high for two internal clock cycles, the mode lines (M[3:0]) are sampled, and the FPGA enters the configuration state. The high during configuration (HDC), low during configuration (LDC), and DONE signals are active outputs in the FPGA's initialization and configuration states. HDC, LDC, and DONE can be used to provide control of external logic signals such as reset, bus enable, or PROM enable during configuration. For parallel master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. If configuration has begun, an assertion of RESET or PRGM initiates an abort, returning the FPGA to the initialization state. The PRGM and RESET pins must be pulled back high before the FPGA will enter the configuration state. During the start-up and operating states, only the assertion of PRGM causes a reconfiguration. In the master configuration modes, the FPGA is the source of configuration clock (CCLK). In this mode, the 56
Configuration
The ORCA Series FPGA functionality is determined by the state of internal configuration RAM. This configuration RAM can be loaded in a number of different modes. In these configuration modes, the FPGA can act as a master or a slave of other devices in the system. The decision as to which configuration mode to use is a system design issue. Configuration is discussed in detail, including the configuration data format and the configuration modes used to load the configuration data in the FPGA, following a description of the start-up state.
Start-Up
After configuration, the FPGA enters the start-up phase. This phase is the transition between the configuration and operational states and begins when the number of CCLKs received after INIT goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. The system design issue in the start-up phase is to ensure the user I/Os become active without inadvertently activating devices in the system or causing bus contention. A second system design concern is the timing of the release of global set/reset of the PLC latches/FFs.
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ORCA Series 4 FPGAs
FPGA States of Operation (continued)
VDD
RESET
PRGM INIT M[3:0] CCLK HDC LDC DONE USER I/O INTERNAL RESET (gsm) INITIALIZATION CONFIGURATION START-UP OPERATION
5-4482(F)
Figure 34. Initialization/Configuration/Start-Up Waveforms
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The default for ORCA is the CCLK_SYNC synchronized start-up mode where DONE is released on the first CCLK rising edge, C1 (see Figure 35). Since this is a synchronized start-up mode, the open-drain DONE signal can be held low externally to stop the occurrence of the other two start-up events. Once the DONE pin has been released and pulled up to a high level, the other two start-up events can be programmed individually to either happen immediately or after up to four rising edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4). The default is for both events to happen immediately after DONE is released and pulled high. A commonly used design technique is to release DONE one or more clock cycles before allowing the I/O to become active. This allows other configuration devices, such as PROMs, to be disconnected using the DONE signal so that there is no bus contention when the I/Os become active. In addition to controlling the FPGA during start-up, other start-up techniques that avoid contention include using isolation devices between the FPGA and other circuits in the system, reassigning I/O locations, and maintaining I/Os as 3-stated outputs until contentions are resolved. Each of these start-up options can be selected during bit stream generation in ORCA Foundry, using Advanced Options. For more information, please see the ORCA Foundry documentation.
FPGA States of Operation (continued)
There are configuration options that control the relative timing of three events: DONE going high, release of the set/reset of internal FFs, and user I/Os becoming active. Figure 35 shows the start-up timing for ORCA FPGAs. The system designer determines the relative timing of the I/Os becoming active, DONE going high, and the release of the set/reset of internal FFs. In the ORCA Series FPGA, the three events can occur in any arbitrary sequence. This means that they can occur before or after each other, or they can occur simultaneously. There are four main start-up modes: CCLK_NOSYNC, CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC. The only difference between the modes starting with CCLK and those starting with UCLK is that for the UCLK modes, a user clock must be supplied to the start-up logic. The timing of start-up events is then based upon this user clock, rather than CCLK. The difference between the SYNC and NOSYNC modes is that for SYNC mode, the timing of two of the start-up events, release of the set/reset of internal FFs, and the I/Os becoming active is triggered by the rise of the external DONE pin followed by a variable number of rising clock edges (either CCLK or UCLK). For the NOSYNC mode, the timing of these two events is based only on either CCLK or UCLK. DONE is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired ANDing. The open-drain DONE signals from multiple FPGAs can be tied together (ANDed) with a pull-up (internal or external) and used as an active-high ready signal, an active-low PROM enable, or a reset to other portions of the system. When used in SYNC mode, these ANDed DONE pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. This signal will not rise until all FPGAs release their DONE pins, allowing the signal to be pulled high.
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FPGA States of Operation (continued)
CCLK PERIOD ORCA CCLK_NOSYNC
F DONE C1 I/O C1 GSRN ACTIVE C1 C2 C2 C3 C3 C4 C4 C2 C3 C4
ORCA CCLK_SYNC
DONE IN DONE I/O C1, C2, C3, OR C4 Di GSRN ACTIVE Di Di + 1 Di + 1 Di + 2 Di + 2 Di + 3 Di + 3 F Di + 4 Di + 4
UCLK
ORCA UCLK_NOSYNC
F
DONE I/O C1 U1 U1 GSRN ACTIVE U1 U2 U2 U2 U3 U3 U3 U4 U4 U4
ORCA UCLK_SYNC
DONE IN DONE I/O C1 U1, U2, U3, OR U4 Di GSRN ACTIVE Di Di + 1 Di + 1 Di + 2 Di + 2 Di + 3 Di + 3 F Di + 4
UCLK PERIOD SYNCHRONIZATION UNCERTAINTY F = FINISHED, NO MORE CLKS REQUIRED.
5-2761(F)
Figure 35. Start-Up Waveforms
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Other bit stream options are also available that allow one portion of the FPGA to remain in operation while a partial reconfiguration is being done. If this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the FPGA and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded.
FPGA States of Operation (continued)
Reconfiguration
To reconfigure the FPGA when the device is operating in the system, a low pulse is input into PRGM or a program command is sent to the system bus. The configuration data in the FPGA is cleared, and the I/Os not used for configuration are 3-stated. The FPGA then samples the mode select inputs and begins reconfiguration. When reconfiguration is complete, DONE is released, allowing it to be pulled high.
Other Configuration Options
There are many other configuration options available to the user that can be set during bit stream generation in ORCA Foundry. These include options to enable boundary scan and/or the MPI and/or the programmable PLL blocks, readback options, and options to control and use the internal oscillator after configuration. Other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, disable the 3-state of I/Os during configuration, and disable the reset of internal RAMs during configuration to allow for partial configurations (see above). For more information on how to set these and other configuration options, please see the ORCA Foundry documentation.
Partial Reconfiguration
All ORCA device families have been designed to allow a partial reconfiguration of the FPGA at any time. This is done by setting a bit stream option in the previous configuration sequence that tells the FPGA to not reset all of the configuration RAM during a reconfiguration. Then only the configuration frames that are to be modified need to be rewritten, thereby reducing the configuration time.
CONFIGURATION DATA 0010 01 01
CONFIGURATION DATA 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
CONFIGURATION DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER 5-5759(F)
Figure 36. Serial Configuration Data Format--Autoincrement Mode
CONFIGURATION DATA 0010 01 00 01
CONFIGURATION DATA 00 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
ADDRESS FRAME 1
CONFIGURATION DATA FRAME 2
ADDRESS FRAME 2
POSTAMBLE
CONFIGURATION HEADER 5-5760(F)
Figure 37. Serial Configuration Data Format--Explicit Mode
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FPGA States of Operation (continued)
Table 36A. Configuration Frame Format and Contents Frame Header Contents 11110010 24-bit length count 11111111 0101 1111 1111 1111 44 reserved bits Part ID Checksum 11111111 1111 0010 11111111 00 14-bit address Checksum 11111111 01 Alignment bits Data bits Checksum 11111111 00 or 10 11111111 111111 11111111 11111111 Description Preamble for generic FPGA. Configuration bit stream length. 8-bit trailing header. ID frame header. Reserved bits set to 0. 20-bit part ID. 8-bit checksum. 8 stop bits (high) to separate frames. This is a new mandatory header for generic portion. 8 stop bits (high) to separate frames. Address frame header. 14-bit address of generic FPGA. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header, same as generic. String of 0 bits added to frame to reach a byte boundary. Number of data bits depends upon device. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header, 00 = finish, 10 = more bits coming. Dummy address. 16 stop bits (high).
ID Frame
FPGA Header FPGA Address Frame FPGA Data Frame
Postamble for Generic FPGA
Table 36B. Configuration Frame Format and Contents for Embedded Block RAM Frame RAM Header RAM Address Frame RAM Data Frame Contents 11110001 11111111 00 6-bit address Checksum 11111111 01 000000 512x18 data bits Checksum 11111111 00 or 10 111111 11111111 11111111 Description A mandatory header for RAM bit stream portion. 8 stop bits (high) to separate frames. Address frame header, same as generic. 6-bit address of RAM blocks. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header, same as generic. Six of 0 bits added to reach a byte boundary. Exact number of bits in a RAM block. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header. 00 = finish, 10 = more bits coming. Dummy address. 16 stop bits (high).
Postamble for RAM
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FPGA States of Operation (continued)
Table 37. Configuration Frame Size Devices Number of Frames Data Bits/Frame Maximum Configuration Data (Number of bits/frame x Number of frames) Maximum PROM Size (bits) (add configuration header and postamble) OR4E2 1796 900 1,610,400 1,161,648 OR4E4 2436 1284 3,127,824 3,128,072 OR4E6 3076 1540 4,737,040 4,737,288 OR4E10 3972 1924 7,642,128 7,642,376 OR4E14 4356 2372 10,332,432 10,332,680
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 4 FPGAs: ID frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry. Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on evaluation of the checksum byte, then a checksum/ parity error is flagged. The checksum is the XOR of all the data bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and data frames. When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will remain in this state until either the RESET or PRGM pins are asserted. Also the pin CFQ_IRQ/MPI_IRQ is forced low to signal the error and the specific type of bit stream error is written to one of the system bus registers by the FPGA configuration logic. The PGRM bit of the system bus control register can also be used to reset out of the error condition and restart configuration.
FPGA Configuration Modes
There are twelve methods for configuring the FPGA. Eleven of the configuration modes are selected on the M0, M1, and M2 inputs. The twelfth configuration mode is accessed through the boundary-scan interface. A fourth input, M3, is used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected or driven to a high state. There are three basic FPGA configuration modes: master, slave, and peripheral. The configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK input. In the three peripheral modes, the FPGA acts as a microprocessor peripheral. Table 38 lists the functions of the configuration mode pins.
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FPGA Configuration Modes (continued)
Table 38. Configuration Modes M3 0 0 0 0 1 1 1 1 1 1 1 1 M2 0 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 0 1 0 0 1 1 0 0 1 1 M0 0 0 1 1 0 1 0 1 0 1 0 1 CCLK Output. High-frequency. Output. High-frequency. Output. High-frequency. NA. Output. Low-frequency. Input. Output. Output. Output. Low-frequency. Output. Low-frequency. Output. Input. Configuration Mode Master Serial Master Parallel Asynchronous Peripheral Reserved Master Serial Slave Parallel MPC860 MPI MPC860 MPI Master Parallel Asynchronous Peripheral MPC860 MPI Slave Serial Data Serial 8-bit 8-bit NA Serial 8-bit 8-bit 16-bit 8-bit 8-bit 32-bit Serial
Master Parallel Mode
The master parallel configuration mode is generally used to interface to industry-standard, bytewide memory. Figure 38 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to memory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor.
DOUT A[21:0] A[21:0] CCLK
TO DAISYCHAINED DEVICES
D[7:0] EPROM
D[7:0] ORCA SERIES FPGA
OE CE
DONE
PROGRAM VDD VDD OR GND
PRGM M2 M1 M0
HDC LDC RCLK
5-9738(F)
Figure 38. Master Parallel Configuration Schematic
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serial ROM's RESET/OE and CE inputs. The serial ROM's RESET/OE is programmable to function with RESET active-high and OE active-low or RESET activelow and OE active-high. In Figure 39, serial ROMs are cascaded to configure multiple daisy-chained FPGAs. The host generates a 500 ns low pulse into the FPGA's PRGM input. The FPGA's INIT input is connected to the serial ROMs' RESET/OE input, which has been programmed to function with RESET active-low and OE active-high. The FPGA DONE is routed to the CE pin. The low on DONE enables the serial ROMs. At the completion of configuration, the high on the FPGA's DONE disables the serial ROM. Serial ROMs can also be cascaded to support the configuration of multiple FPGAs or to load a single FPGA when configuration data requirements exceed the capacity of a single serial ROM. After the last bit from the first serial ROM is read, the serial ROM outputs CEO low and 3-states the DATA output. The next serial ROM recognizes the low on CE input and outputs configuration data on the DATA output. After configuration is complete, the FPGA's DONE output into CE disables the serial ROMs. This FPGA/serial ROM interface is not used in applications in which a serial ROM stores multiple configuration programs. In these applications, the next configuration program to be loaded is stored at the ROM location that follows the last address for the previous configuration program. The reason the interface in Figure 39 will not work in this application is that the low output on the INIT signal would reset the serial ROM address pointer, causing the first configuration to be reloaded. In some applications, there can be contention on the FPGA's DIN pin. During configuration, DIN receives configuration data, and after configuration, it is a user I/O. If there is contention, an early DONE at start-up (selected in ORCA Foundry) may correct the problem. An alternative is to use LDC to drive the serial ROM's CE pin. In order to reduce noise, it is generally better to run the master serial configuration at 1.25 MHz (M3 pin tied high), rather than 10 MHz, if possible.
FPGA Configuration Modes (continued)
In master parallel mode, the starting memory address is 00000 hex, and the FPGA increments the address for each byte loaded. One master mode FPGA can interface to the memory and provide configuration data on DOUT to additional FPGAs in a daisy-chain. The configuration data on DOUT is provided synchronously with the falling edge of CCLK. The frequency of the CCLK output is eight times that of RCLK.
Master Serial Mode
In the master serial mode, the FPGA loads the configuration data from an external serial ROM. The configuration data is either loaded automatically at start-up or on a PRGM command to reconfigure. Serial PROMs can be used to configure the FPGA in the master serial mode. Configuration in the master serial mode can be done at powerup and/or upon a configure command. The system or the FPGA must activate the serial ROM's RESET/OE and CE inputs. At powerup, the FPGA and serial ROM each contain internal power-on reset circuitry that allows the FPGA to be configured without the system providing an external signal. The power-on reset circuitry causes the serial ROM's internal address pointer to be reset. After powerup, the FPGA automatically enters its initialization phase. The serial ROM/FPGA interface used depends on such factors as the availability of a system reset pulse, availability of an intelligent host to generate a configure command, whether a single serial ROM is used or multiple serial ROMs are cascaded, whether the serial ROM contains a single or multiple configuration programs, etc. Because of differing system requirements and capabilities, a single FPGA/serial ROM interface is generally not appropriate for all applications. Data is read in the FPGA sequentially from the serial ROM. The DATA output from the serial ROM is connected directly into the DIN input of the FPGA. The CCLK output from the FPGA is connected to the CLK input of the serial ROM. During the configuration process, CCLK clocks one data bit on each rising edge. Since the data and clock are direct connects, the FPGA/serial ROM design task is to use the system or FPGA to enable the RESET/OE and CE of the serial ROM(s). There are several methods for enabling the
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FPGA Configuration Modes (continued)
TO DAISYCHAINED DEVICES
DATA CLK
DIN CCLK
DOUT
CE RESET/OE CEO
DONE PRGM ORCA SERIES FPGA
DATA CLK
CE RESET/OE CEO TO MORE SERIAL ROMs AS NEEDED PROGRAM
M2 M1 M0
5-4456(F)
Figure 39. Master Serial Configuration Schematic
Asynchronous Peripheral Mode
Figure 40 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessor-peripheral interface. The microprocessor generates the control signals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low CS0 and active-high CS1 chip selects and WR and RD inputs. The chip selects can be cycled or maintained at a static level during the configuration cycle. Each byte of data is written into the FPGA's D[7:0] input pins. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. The FPGA provides an RDY/BUSY status output to indicate that another byte can be loaded. A low on RDY/BUSY indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. The shortest time RDY/BUSY is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. The longest time for RDY/BUSY to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration RAM. The RDY/BUSY status is also available on the D7 pin by enabling the chip selects, setting WR high, and applying RD low, where the RD input provides an output enable for the D7 pin when RD is low. The D[6:0] pins are not enabled to drive when RD is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user can ignore the RDY/BUSY status and simply wait until the maximum time it would take for the RDY/BUSY line to go high, indicating the FPGA is ready for more data, before writing the next data byte.
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FPGA Configuration Modes (continued)
DOUT 8 PRGM D[7:0] RDY/BUSY INIT DONE CCLK
TO DAISYCHAINED DEVICES
MICROPROCESSOR ADDRESS DECODE LOGIC CS0 CS1 RD WR ORCA SERIES FPGA
BUS CONTROLLER
VDD
M2 M1 M0
HDC LDC
5-9739(F)
Figure 40. Asynchronous Peripheral Configuration
Microprocessor Interface Mode
The built-in MPI in Series 4 FPGAs is designed for use in configuring the FPGA. Figure 41 shows the glueless interface for FPGA configuration and readback from the PowerPC processor. When enabled by the mode pins, the MPI handles all configuration/readback control and handshaking with the host processor. For single FPGA configuration, the host sets the configuration control register PRGM bit to zero then back to a one and, after reading that the configuration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA's D[#:0] input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must be set in the configuration control register of the MPI. There are two options for using the host interrupt request in configuration mode. The configuration control register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the FPGA is ready for more configuration data. The MPI status register may be used in conjunction with, or in place of, the interrupt request options. The status register contains a 2-bit field to indicate the bit stream error status. As previously mentioned, there is also a bit to indicate the MPI's readiness to receive another byte of configuration data. A flow chart of the MPI configuration process is shown in Figure 42.
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FPGA Configuration Modes (continued)
8, 16, 32 D[#:0] A[14:31] CLKOUT RD/WR TA POWERPC BDIP IRQx TS
DOUT CCLK D[#:0] A[17:0] MPI_CLK MPI_RW ORCA MPI_ACK SERIES 4 MPI_BDIP FPGA MPI_IRQ MPI_STRB DONE CS0 INIT CS1 HDC LDC
TO DAISYCHAINED DEVICES
BUS CONTROLLER
5-5761(F)
Figure 41. PowerPC/MPI Configuration Schematic Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user mode by setting the MPI_USER_ENABLE bit to 1 in the configuration control register prior to the start of configuration or through a configuration option. To perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the RD_CFG bit to 0 in the configuration control register. Readback data is returned 8 bits at a time to the readback data register and is valid when the DATA_RDY bit of the status register is 1. There is no error checking during readback. A flow chart of the MPI readback operation is shown in Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI readback.
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FPGA Configuration Modes (continued)
POWER ON WITH VALID M[3:0]
WRITE CONFIGURATION CONTROL REGISTER BITS
READ STATUS REGISTER
INIT = 1? YES WRITE CONFIGURATION DATA REGISTER
NO
READ STATUS REGISTER
DONE
YES
DONE = 1? NO
ERROR
YES
BIT STREAM ERROR? NO DATA_RDY = 1? YES WRITE DATA TO CONFIGURATION DATA REG NO
5-5763(F)
Figure 42. Configuration Through MPI
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FPGA Configuration Modes (continued)
ENABLE MICROPROCESSOR INTERFACE IN USER MODE
SET READBACK ADDRESS WRITE RD_CFG TO 0 IN CONTROL REGISTER 1
READ STATUS REGISTER
NO
DATA_RDY = 1? YES READ DATA REGISTER
ERROR
NO
DATA = 0xFF? YES READ DATA REGISTER
ERROR
NO
DATA = 0xFF? YES READ DATA REGISTER
ERROR
NO
START OF FRAME FOUND? YES READ UNTIL END OF FRAME INCREMENT ADDRESS COUNTER IN SOFTWARE
STOP
WRITE RD_CFG TO 1 IN CONTROL REGISTER 1
YES
FINISHED READBACK?
NO
5-5764(F)
Figure 43. Readback Through MPI
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FPGA Configuration Modes (continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple FPGAs are configured in a daisy chain (see the Daisy Chaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in the slave serial mode can be used as the lead device in a daisy chain. Figure 44 shows the connections for the slave serial configuration mode. The configuration data is provided into the FPGA's DIN input synchronous with the configuration clock CCLK input. After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT. CCLK is routed into all slave serial mode devices in parallel. Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the configuration data into the DIN inputs in parallel.
DOUT
TO DAISYCHAINED DEVICES
MICROPROCESSOR OR DOWNLOAD CABLE
INIT PRGM DONE CCLK DIN
ORCA SERIES FPGA
VDD M2 M1 M0 HDC LDC
5-4485(F)
Figure 44. Slave Serial Configuration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. Figure 45 is a schematic of the connections for the slave parallel configuration mode. WR and CS0 are active-low chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to configure multiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can then be used to select the FPGAs to be configured with a given bit stream. The chip selects must be active for each valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor.
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FPGA Configuration Modes (continued)
8 D[7:0] DONE INIT MICROPROCESSOR OR SYSTEM CCLK PRGM VDD CS1 CS0 WR ORCA SERIES FPGA
M2 M1 M0
HDC LDC
5-4487(F)
Figure 45. Slave Parallel Configuration Schematic
Daisy Chaining
Multiple FPGAs can be configured by using a daisy chain of the FPGAs. Daisy chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave parallel mode. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on positive CCLK and out on negative CCLK edges. An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT. The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the negative edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configuration. The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead device and to all of the daisy-chained devices.
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FPGA Configuration Modes (continued)
CCLK A[17:0] A[17:0] DOUT
CCLK DIN DOUT
CCLK DIN DOUT
EPROM
D[7:0] OE CE D[7:0] DONE PRGM PROGRAM VDD VDD OR GND M2 M1 M0
ORCA SERIES FPGA MASTER
DONE INIT HDC LDC RCLK VDD PRGM M2 M1 M0
ORCA SERIES FPGA SLAVE 1
DONE INIT HDC LDC RCLK VDD PRGM M2 M1 M0
ORCA SERIES FPGA SLAVE 2
VDD
INIT HDC LDC RCLK VDD
5-4488(F
Figure 46. Daisy-Chain Configuration Schematic As seen in Figure 46, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be required, depending upon the start-up sequence desired. The loading of configuration data continues after the lead device had received its configuration read into TDI of downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress.
Daisy-Chaining with Boundary Scan
Multiple FPGAs can be configured through the JTAG ports by using a daisy chain of the FPGAs. This daisychaining operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on the positive TCK and out on the negative TCK edges. An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy chain of downstream devices, the lead device loads its configuration data frames.
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Absolute Maximum Ratings (continued)
Table 39. Absolute Maximum Ratings Parameter Storage Temperature Power Supply Voltage with Respect to Ground Input Signal with Respect to Ground Signal Applied to High-impedance Output Maximum Package Body Temperature Symbol Tstg VDD3 VDD15 -- -- -- Min -65 -- -- VSS - 0.3 VSS - 0.3 -- Max 150
4.2
Unit C V V V V C
2 VDDIO + 0.3 VDDIO + 0.3 220
Recommended Operating Conditions
Table 40. Recommended Operating Conditions Parameter Power Supply Voltage with Respect to Ground Input Voltages Junction Temperature Symbol VDD3 VDD15 VIN TJ Min 2.7 1.4 VSS - 0.3 -40 Max 3.6 1.6 VDDIO + 0.3 125 Unit V V V C
Note: The maximum recommended junction temperature (TJ) during operation is 125 C.
Electrical Characteristics
Table 41. Electrical Characteristics Parameter Input Leakage Current Standby Current: OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Standby Current: OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Powerup Current: OR4E2 OR4E4 OR4E6 OR4E10 OR4E14 Symbol IL IDDSB Test Conditions VDD = max, VIN = VSS or VDD TA = 25 C, VDD = 3.3 V internal oscillator running, no output loads, inputs VDD or GND (after configuration) Min -10 -- -- -- -- -- -- -- -- -- -- Max Unit 10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD -- -- -- -- -- A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
IDDSB
TA = 25 C, VDD = 3.3 V internal oscillator stopped, no output loads, inputs VDD or GND (after configuration)
Ipp
Power supply current at approximately 1 V, within a recommended power supply ramp rate of TBD 1 ms--200 ms TBD TBD TBD TBD
* The pull-up resistor will externally pull the pin to a level 1.0 V below VDDIO.
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Electrical Characteristics (continued)
Table 41. Electrical Characteristics (continued) Parameter Data Retention Voltage (VDD33) Input Capacitance Output Capacitance DONE Pull-up Resistor* M[3:0] Pull-up Resistor* I/O Pad Static Pull-up Current* I/O Pad Static Pull-down Current I/O Pad Pull-up Resistor* I/O Pad Pull-down Resistor DONE Pull-up Resistor* M[3:0] Pull-up Resistor* I/O Pad Static Pull-up Current* I/O Pad Static Pull-down Current I/O Pad Pull-up Resistor* I/O Pad Pull-down Resistor Symbol VDR CIN COUT RDONE RM IPU IPD RPU RPD RDONE RM IPU IPD RPU RPD Test Conditions TA = 25 C TA = 25 C, VDD = 3.3 V Test frequency = 1 MHz TA = 25 C, VDD = 3.3 V Test frequency = 1 MHz -- -- VDDIO = 3.6 V, VIN = VSS, TA = 0 C VDDIO = 3.6 V, VIN = VSS, TA = 0 C VDDIO = all, VIN = VSS, TA = 0 C VDDIO = all, VIN = VDD, TA = 0 C -- -- VDDIO = 3.6 V, VIN = VSS, TA = 0 C VDDIO = 3.6 V, VIN = VSS, TA = 0 C VDDIO = all, VIN = VSS, TA = 0 C VDDIO = all, VIN = VDD, TA = 0 C Min 2.3 -- -- 100 100 Max Unit -- 6 6 -- -- V pF pF k k A A k k k k A A k k
14.4 50.9 26 100 50 100 100 103 -- -- -- --
14.4 50.9 26 100 50 103 -- --
* The pull-up resistor will externally pull the pin to a level 1.0 V below VDDIO.
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Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. Table 42. Pin Descriptions Symbol Dedicated Pins VDD33 VDD15 VDDIO GND PLL_VF PTEMP
RESET
I/O -- 3 V positive power supply.
Description
-- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground supply. -- Dedicated pins for PLL filtering. I I Temperature-sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after configuration.* As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. This pin always has an active pull-up.
CCLK
I O
DONE
I O
PRGM RD_CFG
I I
This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0.
RD_DATA/TDO
CFG_IRQ/MPI_IRQ
O O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary-scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral configuration assertion by the FPGA on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Pin Information (continued)
Table 42. Pin Descriptions (continued)
Symbol M[3:0] I/O I Description During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
Special-Purpose Pins (Can also be used as a general I/O)
I/O After configuration, these pins are user-programmable I/O.* PLL_CK[0:7] I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by PLLs.
P[TBTR]CLK[1:0][ I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential TC] pairing. They may be used as general I/O pins if not needed for clocking purposes. TDI, TCK, TMS I If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O.* RDY/BUSY/RCLK O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* I/O During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. HDC O High during configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* LDC O Low during configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.* I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe.
CS0, CS1
I/O After configuration, these pins are user-programmable I/O pins.* RD/MPI_STRB I
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Pin Information (continued)
Table 42. Pin Descriptions (continued)
Symbol A[17:0] I/O I Description During MPI mode, the A[17:0] are used as the address bus driven by the PowerPC bus master utilizing the least significant bits of the PowerPC 32-bit address.
Special-Purpose Pins (continued)
O During master parallel configuration mode, A[17:0] address the configuration EPROM. In MPI mode, many of the A[n] pins have alternate uses as described below. See the Special Function Blocks section for more MPI information. During configuration, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled. MPI_BURST MPI_BDIP I I A[21] is used as the MPI_BURST. It is driven low to indicate a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. A[22] is used as the MPI_BDIP It is driven by the PowerPC processor. Assertion of this pin . indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. A[19:18] are used as the MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[21:0], address the configuration EPROMs up to 4M bytes.
MPI_TSZ[1:0]
I
A[21:0] MPI_ACK MPI_CLK
O If not used for MPI, these pins are user-programmable I/O pins.* O In PowerPC mode MPI operation, this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA bus clock.
MPI_TEA MPI_RTRY D[31:0]
O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. O This pin requests the MPC860 to relinquish the bus and retry the cycle. I/O Selectable data bus width from 8, 16, 32 bits. Driven by the bus master in a write transaction. Driven by MPI in a read transaction. I D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low. After configuration, the pins are user-programmable I/O pins.*
DP[3:0]
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[7:0], DP[1] for D[15:8], DP[2] for D[23:16], and DP[3] for D[32:24]. After configuration, this pin is a user-programmable I/O pin.* I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled.
DIN
I/O After configuration, this pin is a user-programmable I/O pin.* DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK. I/O After configuration, DOUT is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Pin Information (continued)
Package Compatibility
Table 43 provides the number of user I/Os available for the ORCA Series 4 FPGAs for each available package. Each package has seven dedicated configuration pins. Table 44 through Table 46 provide the package pin and pin function for the ORCA Series 4 FPGAs and packages. The bond pad name is identified in the PIO nomenclature used in the ORCA Foundry design editor. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the FPGA. The tables provide no information on unused pads. Table 43. ORCA I/Os Summary Device OR4E2/OR4E4/OR4E6 User I/O Single Ended Available Differential Pairs (LVDS, LVPECL) Configuration Dedicated Function VDD15 VDD33 VDDIO VSS 262 128 7 3 16 8 24 68 306 150 7 3 40 8 24 44 466 196 7 3 48 8 60 88 352 PBGA 432 EBGA 680 PBGAM1
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Pin Information (continued)
As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:
s s s s
_A1 indicates one ball between pairs. _A2 indicates two balls between pairs. _D0 indicates balls are diagonally adjacent. _D1 indicates diagonally adjacent separated by one physical ball.
VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank). Table 44. 352-Pin PBGA Pinout
352 BGA Ball D12 B10 A10 D10 B9 C10 A9 B8 A8 C9 B7 D8 A7 C8 B6 D7 A6 B5 A5 C6 B4 D5 A4 E2 E4 E3 E1 F2 VDDIO Bank TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL VREF Group 1 1 1 1 2 2 2 2 2 2 3 3 3 4 4 4 4 5 5 5 5 6 6 7 7 7 7 8 General-Purpose User I/O OR4E2 PT11D PT11C PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A PT8B PT7D PT7C PT7B PT7A PT6D PT6C PT5D PT5C PT4D PT4C PT2D PT2C PL2D PL2C PL3D PL3C PL4D OR4E4 PT13D PT13C PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A PT9D PT8D PT8C PT7D PT7C PT6D PT6C PT5D PT5C PT4D PT4C PT2D PT2C PL2D PL2C PL4D PL4C PL5D OR4E6 PT18D PT18C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT11D PT10D PT10C PT9D PT9C PT8D PT8C PT6D PT6C PT4D PT4C PT2D PT2C PL2D PL2C PL4D PL4C PL6D Additional Function MPI_RTRY MPI_ACK M0 M1 MPI_CLK A21/MPI_BURST M2 M3 VREF_TL_02 MPI_TEA VREF_TL_03 D0 TMS A20/MPI_BDIP A19/MPI_TSZ1 A18/MPI_TSZ0 D3 D1 D2 TDI TCK PLL_CK1C/PPLL PLL_CK1T/PPLL PLL_CK0C/ HPPLL PLL_CK0T/ HPPLL D5 D6 HDC Pair Differential
L1C_D2 L1T_D2 L2C_A2 L2T_A2 L3C_D0 L3T_D0 L4C_D0 L4T_D0 L5C_D1 L5T_D1 -- L6C_D2 L6T_D2 L7C_D2 L7T_D2 L8C_D2 L8T_D2 L9C_A0 L9T_A0 L10C_D2 L10T_D2 L11C_D2 L11T_D2 L12C_A1 L12T_A1 L13C_A1 L13T_A1 L14C_D1
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
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Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball G4 F3 F1 G1 G3 H2 J4 H1 H3 J2 J1 B1 C2 C1 D2 D3 D1 G2 C11 C7 C5 B3 C4 A3 A1 A2 A26 AC13 AC18 AC23 AC4 AC8 AD24 AA23 AA4 A19 C19 B18 A18 B17 C18 A17 D17 VDDIO Bank TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TC TC TC TC TC TC TC TC VREF Group 8 9 9 9 9 9 9 10 10 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 2 General-Purpose User I/O OR4E2 PL4C PL5D PL5C PL5B PL5A PL6D PL6C PL7D PL7C PL7B PL7A VDD33 PRD_DATA PRESET PRD_CFG PPRGRM VDDIO_TL VDDIO_TL VDDIO_TL VDDIO_TL PCFG_MPI_IRQ PCCLK PDONE VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PT21D PT21C PT20D PT20C PT20B PT20A PT19D PT19C OR4E4 PL5C PL6D PL6C PL7D PL7C PL8D PL8C PL10D PL10C PL11D PL11C VDD33 PRD_DATA PRESET PRD_CFG PPRGRM VDDIO_TL VDDIO_TL VDDIO_TL VDDIO_TL PCFG_MPI_IRQ PCCLK PDONE VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PT28D PT28C PT27D PT27C PT27B PT27A PT26D PT26C OR4E6 PL6C PL8D PL8C PL9D PL9C PL10D PL10C PL12D PL12C PL13D PL13C VDD33 PRD_DATA PRESET PRD_CFG PPRGRM VDDIO_TL VDDIO_TL VDDIO_TL VDDIO_TL PCFG_MPI_IRQ PCCLK PDONE VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PT35D PT35C PT34D PT34C PT33D PT33C PT32D PT32C Additional Function LDC -- D7 VREF_TL_09 A17 CS0 CS1 INIT DOUT VREF_TL_10 A16 -- TDO -- -- -- -- -- -- -- CFG_IRQ/ MPI_IRQ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_TC_01 -- -- -- -- VREF_TC_02 Pair Differential
L14T_D1 L15C_A1 L15T_A1 L16C_A1 L16T_A1 L17C_D1 L17T_D1 L18C_A1 L18T_A1 L19C_A0 L19T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_A1 L1T_A1 L2C_A0 L2T_A0 L3C_D0 L3T_D0 L4C_A2 L4T_A2
TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE
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Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball B16 C17 B15 A15 C16 B14 D15 A14 C15 B13 A13 C14 B12 C13 A12 B11 C12 A11 A16 D13 R15 R16 T11 T12 T13 T14 T15 T16 T23 T4 J24 G25 H23 G26 H24 F25 G23 F26 E25 E26 F24 D25 VDDIO Bank TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TR TR TR TR TR TR TR TR TR TR TR TR VREF Group 2 2 3 3 3 3 4 4 4 4 5 5 5 5 5 5 6 6 -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 2 2 2 3 3 General-Purpose User I/O OR4E2 PT18D PT18C PT18B PT18A PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT13B PT13A PT12B PT12A VDDIO_TC VDDIO_TC VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR8C PR8D PR7A PR7B PR7C PR7D PR6A PR6B PR6C PR6D PR5C PR5D OR4E4 PT25D PT25C PT24D PT24C PT23D PT23C PT21D PT21C PT19D PT19C PT18D PT18C PT17D PT17C PT16D PT16C PT14D PT14C VDDIO_TC VDDIO_TC VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR11C PR11D PR10C PR10D PR9C PR9D PR8C PR8D PR7C PR7D PR6C PR6D OR4E6 PT30D PT30C PT29D PT29C PT28D PT28C PT26D PT26C PT24D PT24C PT23D PT23C PT22D PT22C PT21D PT21C PT19D PT19C VDDIO_TC VDDIO_TC VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR13C PR13D PR12C PR12D PR11C PR11D PR10C PR10D PR9C PR9D PR7C PR7D Additional Function -- -- -- VREF_TC_03 -- -- -- -- -- VREF_TC_04 PTCK1C PTCK1T PTCK0C PTCK0T VREF_TC_05 -- -- VREF_TC_06 -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_TR_01 -- -- -- -- -- -- VREF_TR_02 -- -- VREF_TR_03 Pair Differential
L5C_D0 L5T_D0 L6C_A0 L6T_A0 L7C_D1 L7T_D1 L8C_D2 L8T_D2 L9C_D1 L9T_D1 L10C_D1 L10T_D1 L11C_D0 L11T_D0 L12C_D0 L12T_D0 L13C_D1 L13T_D1 -- -- -- -- -- -- -- -- -- -- -- -- L1T_D1 L1C_D1 L2T_D2 L2C_D2 L3T_D1 L3C_D1 L4T_D2 L4C_D2 L5T_A0 L5C_A0 L6T_D1 L6C_D1
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
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Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball E23 D26 E24 VDDIO Bank TR TR TR VREF Group 3 3 4 General-Purpose User I/O OR4E2 PR4C PR4D PR3C OR4E4 PR5C PR5D PR3C OR4E6 PR5C PR5D PR3C Additional Function -- -- PLL_CK3T/ PLL1(1.554/ 2.048 MHz) PLL_CK3C/ PLL1(1.554/ 2.048 MHz) PLL_CK2C/PPLL PLL_CK2T/PPLL VREF_TR_05 -- -- -- VREF_TR_06 -- -- VREF_TR_07 -- -- -- VREF_TR_08 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair Differential
L7T_D2 L7C_D2 L8T_D1
TRUE COMPLEMENT TRUE
C25
TR
4
PR3D
PR3D
PR3D
L8C_D1
COMPLEMENT
A24 B23 C23 A23 B22 D22 C22 A22 B21 D20 A21 B20 A20 C20 B19 D18 G24 D24 C26 A25 B24 C21 P12 P13 P14 P15 P16 R11 R12 R13 R14 L23 L4 V25
TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR CR
5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1
PT27D PT27C PT26D PT26C PT26B PT26A PT25D PT25C PT24D PT24C PT24B PT24A PT23D PT23C PT22D PT22C VDDIO_TR VDDIO_TR VDD33 VDD33 PLL_VF VDDIO_TR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR20C
PT37D PT37C PT36D PT36C PT35B PT35A PT34D PT34C PT33D PT33C PT32D PT32C PT31D PT31C PT29D PT29C VDDIO_TR VDDIO_TR VDD33 VDD33 PLL_VF VDDIO_TR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR29C
PT47D PT47C PT45D PT45C PT43D PT43C PT42D PT42C PT40D PT40C PT39D PT39C PT38D PT38C PT36D PT36C VDDIO_TR VDDIO_TR VDD33 VDD33 PLL_VF VDDIO_TR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PR35C
L9C_A0 L9T_A0 L10C_A1 L10T_A1 L11C_A1 L11T_A1 L12C_A1 L12T_A1 L13C_D1 L13T_D1 L14C_D0 L14T_D0 L15C_A1 L15T_A1 L16C_D1 L16T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1T_A0
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE
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Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball V26 U25 V24 U23 T25 U24 T26 R25 R26 T24 P25 R23 P26 N25 N23 N26 P24 M25 N24 M26 L25 M24 L26 K25 L24 K26 K23 J25 K24 J26 H25 H26 U26 R24 M23 M16 N11 N12 N13 N14 N15 N16 VDDIO Bank CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR VREF Group 1 1 1 2 2 2 2 3 3 4 4 4 4 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 -- -- -- -- -- -- -- -- -- -- General-Purpose User I/O OR4E2 PR20D PR19C PR19D PR18C PR18D PR17A PR17B PR17C PR17D PR16C PR16D PR15A PR15B PR15C PR15D PR14A PR14B PR14C PR14D PR13C PR13D PR12A PR12B PR12C PR12D PR11B PR11C PR11D PR10C PR10D PR9C PR9D VDDIO_CR VDDIO_CR VDDIO_CR VSS VSS VSS VSS VSS VSS VSS OR4E4 PR29D PR28C PR28D PR26A PR26B PR25A PR25B PR25C PR25D PR23C PR23D PR22C PR22D PR21C PR21D PR20C PR20D PR19C PR19D PR17C PR17D PR16C PR16D PR15C PR15D PR14B PR14C PR14D PR13C PR13D PR12C PR12D VDDIO_CR VDDIO_CR VDDIO_CR VSS VSS VSS VSS VSS VSS VSS OR4E6 PR35D PR33C PR33D PR31C PR31D PR30C PR30D PR29C PR29D PR27C PR27D PR26C PR26D PR25C PR25D PR24C PR24D PR23C PR23D PR21C PR21D PR20C PR20D PR19C PR19D PR18D PR17C PR17D PR15C PR15D PR14C PR14D VDDIO_CR VDDIO_CR VDDIO_CR VSS VSS VSS VSS VSS VSS VSS Additional Function -- VREF_CR_01 -- -- VREF_CR_02 -- -- -- VREF_CR_03 PRCK1T PRCK1C -- VREF_CR_04 -- -- PRCK0T PRCK0C VREF_CR_05 -- -- VREF_CR_06 -- -- -- -- -- VREF_CR_07 -- -- -- VREF_CR_08 -- -- -- -- -- -- -- -- -- -- -- Pair Differential
L1C_A0 L2T_D0 L2C_D0 L3T_D1 L3C_D1 L4T_D1 L4C_D1 L5T_A0 L5C_A0 L6T_D1 L6C_D1 L7T_D2 L7C_D2 L8T_A1 L8C_A1 L9T_D1 L9C_D1 L10T_D0 L10C_D0 L11T_D0 L11C_D0 L12T_D1 L12C_D1 L13T_D0 L13C_D0 -- L14T_D1 L14C_D1 L15T_D1 L15C_D1 L16T_A0 L16C_A0 -- -- -- -- -- -- -- -- -- --
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT -- -- -- -- -- -- -- -- -- --
Lucent Technologies Inc.
83
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball P11 F23 F4 AE20 AC19 AF20 AD19 AE21 AC20 AD20 AE22 AF22 AD21 AE23 AC22 AF23 AD22 AE24 AD23 AD26 AC25 AC24 AC26 AB25 AB23 AB26 AA25 Y23 AA24 AA26 Y25 Y26 Y24 W25 V23 W26 W24 AF21 AF24 AE26 VDDIO Bank CR CR CR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR VREF Group -- -- -- 1 1 1 1 1 1 2 2 2 3 3 3 3 3 4 4 5 5 5 5 6 6 6 6 7 7 7 7 7 7 8 8 8 8 -- -- -- General-Purpose User I/O OR4E2 VSS VDD15 VDD15 PB22A PB22B PB22C PB22D PB23A PB23B PB23C PB23D PB24C PB25A PB25C PB25D PB26C PB26D PB27C PB27D PR26A PR26B PR25A PR25B PR25C PR25D PR24C PR24D PR23A PR23B PR23C PR23D PR22A PR22B PR22C PR22D PR21C PR21D VDDIO_BR VDD33 VDD33 OR4E4 VSS VDD15 VDD15 PB30C PB30D PB31C PB31D PB32C PB32D PB33C PB33D PB34C PB35A PB35C PB35D PB36C PB36D PB37C PB37D PR38A PR38B PR37C PR37D PR36C PR36D PR35C PR35D PR34C PR34D PR33C PR33D PR32C PR32D PR31C PR31D PR30C PR30D VDDIO_BR VDD33 VDD33 OR4E6 VSS VDD15 VDD15 PB37C PB37D PB38C PB38D PB39C PB39D PB40C PB40D PB42C PB43A PB44C PB44D PB45C PB45D PB47C PB47D PR46C PR46D PR44C PR44D PR43C PR43D PR41C PR41D PR40C PR40D PR39C PR39D PR38C PR38D PR37C PR37D PR36C PR36D VDDIO_BR VDD33 VDD33 Additional Function -- -- -- -- -- VREF_BR_01 -- -- -- -- VREF_BR_02 -- -- -- VREF_BR_03 -- -- PLL_CK5T/PPLL PLL_CK5C/PPLL
PLL_CK4T/PLL2 (155.52 MHz) PLL_CK4C/PLL2 (155.52 MHz)
Pair
Differential
-- -- -- L1T_D1 L1C_D1 L2T_D1 L2C_D1 L3T_D1 L3C_D1 L4T_D1 L4C_D1 -- -- L5T_D1 L5C_D1 L6T_D1 L6C_D1 L7T_D0 L7C_D0 L8T_D0 L8C_D0 L9T_A1 L9C_A1 L10T_A1 L10C_A1 L11T_D0 L11C_D0 L12T_D0 L12C_D0 L13T_D0 L13C_D0 L14T_A1 L14C_A1 L15T_D1 L15C_D1 L16T_A1 L16C_A1 -- -- --
-- -- -- TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT -- -- --
VREF_BR_05 -- -- -- VREF_BR_06 -- -- -- -- VREF_BR_07 -- -- -- VREF_BR_08 -- -- -- -- --
84
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball AD25 AB24 L13 L14 L15 L16 M11 M12 M13 M14 M15 D21 D6 AD11 AE13 AC12 AF13 AD12 AE14 AF14 AD13 AE15 AD14 AF15 AE16 AD15 AF16 AC15 AE17 AF17 AC17 AE18 AD17 AF18 AE19 AF19 AD18 AC14 AD16 H4 J23 N4 VDDIO Bank BR BR BR BR BR BR BR BR BR BR BR BR BR BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC VREF Group -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 2 2 2 2 3 3 3 3 3 3 4 4 4 4 5 5 5 5 6 6 -- -- -- -- -- General-Purpose User I/O OR4E2 VDDIO_BR VDDIO_BR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PB13A PB13B PB13C PB13D PB14C PB14D PB15C PB15D PB16C PB16D PB17A PB17B PB17C PB17D PB18A PB18B PB18C PB18D PB19C PB19D PB20C PB20D PB21A PB21B VDDIO_BC VDDIO_BC VSS VSS VSS OR4E4 VDDIO_BR VDDIO_BR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PB17C PB17D PB18C PB18D PB19C PB19D PB20C PB20D PB21C PB21D PB22C PB22D PB23C PB23D PB24C PB24D PB25C PB25D PB26C PB26D PB27C PB27D PB28C PB28D VDDIO_BC VDDIO_BC VSS VSS VSS OR4E6 VDDIO_BR VDDIO_BR VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PB21C PB21D PB22C PB22D PB23C PB23D PB24C PB24D PB26C PB26D PB27C PB27D PB28C PB28D PB29C PB29D PB30C PB30D PB32C PB32D PB34C PB34D PB35C PB35D VDDIO_BC VDDIO_BC VSS VSS VSS Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_BC_01 -- PBCK0T PBCK0C VREF_BC_02 -- -- VREF_BC_03 -- -- PBCK1T PBCK1C -- -- -- VREF_BC_04 -- VREF_BC_05 -- -- -- VREF_BC_06 -- -- -- -- -- Pair Differential
-- -- -- -- -- -- -- -- -- -- -- -- -- L1T_D1 L1C_D1 L2T_D2 L2C_D2 L3T_D1 L3C_D1 L4T_D1 L4C_D1 L5T_D0 L5C_D0 L6T_D0 L6C_D0 L7T_D1 L7C_D1 L8T_D1 L8C_D1 L9T_A2 L9C_A2 L10T_D0 L10C_D0 L11T_D0 L11C_D0 L12T_D1 L12C_D1 -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT -- -- -- -- --
Lucent Technologies Inc.
85
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball P23 V4 W23 L11 L12 D11 D16 Y1 W3 AA2 Y4 AA1 AB2 AB1 AA3 AC2 AB4 AC1 AE3 AF3 AE4 AD4 AF4 AE5 AC5 AF5 AE6 AC7 AD6 AF6 AE7 AF7 AD7 AE8 AC9 AF8 AD8 AE9 AF9 AE10 VDDIO Bank BC BC BC BC BC BC BC BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL VREF Group -- -- -- -- -- -- -- 1 1 1 1 2 3 3 3 3 4 4 5 5 5 5 5 6 6 7 7 7 7 7 7 8 8 8 8 9 9 9 9 10 General-Purpose User I/O OR4E2 VSS VSS VSS VSS VSS VDD15 VDD15 PL22D PL22C PL22B PL22A PL23C PL24D PL24C PL25D PL25C PL27D PL27C PB2A PB2C PB2D PB3C PB3D PB4C PB4D PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7B PB7C PB7D PB8C PB8D PB9C PB9D PB10C OR4E4 VSS VSS VSS VSS VSS VDD15 VDD15 PL32D PL32C PL33D PL33C PL34C PL35B PL35A PL36B PL36A PL39D PL39C PB2A PB2C PB2D PB4A PB4B PB5C PB5D PB6C PB6D PB7C PB7D PB8C PB8D PB9C PB9D PB10C PB10D PB11C PB11D PB12C PB12D PB13C OR4E6 VSS VSS VSS VSS VSS VDD15 VDD15 PL38D PL38C PL39D PL39C PL40C PL42D PL42C PL44D PL44C PL47D PL47C PB2A PB2C PB2D PB4C PB4D PB6C PB6D PB8C PB8D PB9C PB9D PB10C PB10D PB11C PB11D PB12C PB12D PB13C PB13D PB14C PB14D PB16C Additional Function -- -- -- -- -- -- -- D8 VREF_BL_01 D9 D10 VREF_BL_02 D11 D12 VREF_BL_03 D13 PLL_CK7C/ HPPLL PLL_CK7T/ HPPLL DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_BL_05 DP3 VREF_BL_06 D14 D15 D16 D17 D18 VREF_BL_07 D19 D20 D21 VREF_BL_08 D22 D23 D24 VREF_BL_09 D25 D26 Pair Differential
-- -- -- -- -- -- -- L1C_D1 L1T_D1 L2C_D1 L2T_D1 -- L3C_A0 L3T_A0 L4C_D1 L4T_D1 L5C_D2 L5T_D2 -- L6T_A0 L6C_A0 L7T_A1 L7C_A1 L8T_A1 L8C_A1 L9T_D0 L9C_D0 L10T_D0 L10C_D0 L11T_D0 L11C_D0 L12T_A1 L12C_A1 L13T_D1 L13C_D1 L14T_A1 L14C_A1 L15T_A0 L15C_A0 L16T_D0
-- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball AD9 AC10 AE11 AD10 AF11 AE12 AF12 Y3 AB3 AD2 AC3 AD1 AF2 AD5 AF10 B25 B26 C24 C3 D14 D19 D23 D4 D9 AC21 AC6 K2 J3 K1 K4 L2 K3 M2 M1 L3 N2 M4 N1 M3 P2 P1 VDDIO Bank BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL VREF Group 10 10 10 11 11 11 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 2 2 2 2 3 3 4 4 4 4 5 General-Purpose User I/O OR4E2 PB10D PB11C PB11D PB12A PB12B PB12C PB12D VDDIO_BL PTEMP VDDIO_BL LVDS_R VDD33 VDD33 VDDIO_BL VDDIO_BL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PL8D PL8C PL9D PL9C PL10D PL10C PL10B PL10A PL11B PL11A PL13D PL13C PL14D PL14C PL15D OR4E4 PB13D PB14C PB14D PB15C PB15D PB16C PB16D VDDIO_BL PTEMP VDDIO_BL LVDS_R VDD33 VDD33 VDDIO_BL VDDIO_BL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PL12D PL12C PL13D PL13C PL14D PL14C PL15D PL15C PL17D PL17C PL19D PL19C PL20D PL20C PL21D OR4E6 PB16D PB18C PB18D PB19C PB19D PB20C PB20D VDDIO_BL PTEMP VDDIO_BL LVDS_R VDD33 VDD33 VDDIO_BL VDDIO_BL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 PL14D PL14C PL16D PL16C PL18D PL18C PL19D PL19C PL21D PL21C PL23D PL23C PL24D PL24C PL25D Additional Function D27 VREF_BL_10 D28 D29 D30 VREF_BL_11 D31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A15 A14 VREF_CL_01 D4 RDY/BUSY/ RCLK VREF_CL_02 A13 A12 A11 VREF_CL_03 RD/MPI_STRB VREF_CL_04 PLCK0C PLCK0T A10 Pair Differential
L16C_D0 L17T_D1 L17C_D1 L18T_D1 L18C_D1 L19T_A0 L19C_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_D0 L1T_D0 L2C_A2 L2T_A2 L3C_D0 L3T_D0 L4C_A0 L4T_A0 L5C_D1 L5T_D1 L6C_D2 L6T_D2 L7C_D1 L7T_D1 L8C_D1
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
Lucent Technologies Inc.
87
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 44. OR4E6 352-Pin PBGA Pinout (continued)
352 BGA Ball N3 R2 P3 R1 T2 R3 T1 R4 U2 U1 U4 V2 U3 V1 W2 W1 V3 Y2 W4 L1 P4 T3 AD3 AE1 AE2 AE25 AF1 AF25 AF26 B2 AC11 AC16 VDDIO Bank CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL VREF Group 5 5 5 6 6 6 6 6 6 7 7 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- General-Purpose User I/O OR4E2 PL15C PL16D PL16C PL17D PL17C PL17B PL17A PL18D PL18C PL19D PL19C PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A VDDIO_CL VDDIO_CL VDDIO_CL VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 OR4E4 PL21C PL22D PL22C PL24D PL24C PL25D PL25C PL26D PL26C PL27D PL27C PL28D PL28C PL29D PL29C PL30D PL30C PL31D PL31C VDDIO_CL VDDIO_CL VDDIO_CL VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 OR4E6 PL25C PL26D PL26C PL28D PL28C PL29D PL29C PL30D PL30C PL32D PL32C PL34D PL34C PL35D PL35C PL36D PL36C PL37D PL37C VDDIO_CL VDDIO_CL VDDIO_CL VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 Additional Function A9 A8 VREF_CL_05 PLCK1C PLCK1T VREF_CL_06 A7 A6 A5 WR/MPI_RW VREF_CL_07 A4 VREF_CL_08 A3 A2 A1 A0 DP0 DP1 -- -- -- -- -- -- -- -- -- -- -- -- -- Pair Differential
L8T_D1 L9C_D0 L9T_D0 L10C_D0 L10T_D0 L11C_D1 L11T_D1 L12C_D1 L12T_D1 L13C_A2 L13T_A2 L14C_D1 L14T_D1 L15C_D0 L15T_D0 L16C_D1 L16T_D1 L17C_D1 L17T_D1 -- -- -- -- -- -- -- -- -- -- -- -- --
TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- --
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Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:
s s s s
_A1 indicates one ball between pairs. _A2 indicates two balls between pairs. _D0 indicates balls are diagonally adjacent. _D1 indicates diagonally adjacent separated by one physical ball.
VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank). Table 45. 432-Pin EBGA
432 BGA Ball B19 C19 D19 C20 A21 B21 A22 B22 C22 A23 D20 C21 B23 D22 C23 B24 C24 D23 A25 B25 D24 A26 B26 C26 A27 B27 C27 D26 F31 H28 E30 E31 VDDIO VREF Bank Group 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 General-Purpose User I/O OR4E2 PT11D PT11C PT11B PT11A PT10D PT10C PT9D PT9C PT9B PT9A PT10B PT10A PT8B PT8A PT7D PT7C PT7B PT7A PT6D PT6C PT5D PT5C PT4D PT4C PT3D PT3C PT2D PT2C PL3D PL3C PL2D PL2C OR4E4 PT13D PT13C PT13B PT13A PT12D PT12C PT11D PT11C PT11B PT11A PT12B PT12A PT9D PT9C PT8D PT8C PT7D PT7C PT6D PT6C PT5D PT5C PT4D PT4C PT3D PT3C PT2D PT2C PL4D PL4C PL2D PL2C OR4E6 PT18D PT18C PT17D PT17C PT16D PT16C PT14D PT14C PT13D PT13C PT15D PT15C PT11D PT11C PT10D PT10C PT9D PT9C PT8D PT8C PT6D PT6C PT4D PT4C PT3D PT3C PT2D PT2C PL4D PL4C PL2D PL2C Additional Function
MPI_RTRY MPI_ACK
Pair
Differential
L1C_A0 L1T_A0 L2C_D0 L2T_D0 L3C_A0 L3T_A0 L5C_A0 L5T_A0 L6C_D1 L6T_D1 L4C_D0 L4T_D0 L7C_D1 L7T_D1 L8C_D0 L8T_D0 L9C_D0 L9T_D0 L10C_A0 L10T_A0 L11C_D2 L11T_D2 L12C_A0 L12T_A0 L13C_A0 L13T_A0 L14C_D0 L14T_D0 L17C_D2 L17T_D2 L15C_A0 L15T_A0
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE
-- VREF_TL_01 M0 M1 M2 M3 VREF_TL_02
MPI_TEA
MPI_CLK A21/MPI_BURST VREF_TL_03 -- D0 TMS
A20/MPI_BDIP
A19/MPI_TSZ1 A18/MPI_TSZ0 D3 D1 D2 TDI TCK -- VREF_TL_06 PLL_CK1C PLL_CK1T D5 D6 PLL_CK0C PLL_CK0T
Lucent Technologies Inc.
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ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball F29 F30 G29 G30 K28 J30 G31 J28 H30 J29 K30 K31 L29 M28 J31 K29 A12 A16 A2 A20 A24 A29 H29 E29 C25 B20 E28 D27 A1 A31 AA28 AA4 AE28 D30 D29 D31 F28 C28 A28 B28 A9 C10 B10 A10 VDDIO VREF Bank Group 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 7 8 8 9 9 9 9 9 9 10 10 10 10 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 General-Purpose User I/O OR4E2 PL2B PL2A PL4D PL4C PL6D PL6C PL5D PL5C PL5B PL5A PL7D PL7C PL7B PL7A PL6B PL6A VSS VSS VSS VSS VSS VSS VDDIO0_TL VDDIO0_TL VDDIO0_TL VDDIO0_TL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15
PRESET
OR4E4 PL3D PL3C PL5D PL5C PL8D PL8C PL6D PL6C PL7D PL7C PL10D PL10C PL11D PL11C PL9D PL9C VSS VSS VSS VSS VSS VSS VDDIO0_TL VDDIO0_TL VDDIO0_TL VDDIO0_TL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15
PRESET
OR4E6 PL3D PL3C PL6D PL6C PL10D PL10C PL8D PL8C PL9D PL9C PL12D PL12C PL13D PL13C PL11D PL11C VSS VSS VSS VSS VSS VSS VDDIO0_TL VDDIO0_TL VDDIO0_TL VDDIO0_TL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15
PRESET
Additional Function -- VREF_TL_07 HDC
LDC CS0
Pair
Differential
L16C_A0 L16T_A0 L18C_A0 L18T_A0 L21C_D1 L21T_D1 L19C_D2 L19T_D2 L20C_D0 L20T_D0 L23C_A0 L23T_A0 L24C_D0 L24T_D0 L22C_D1 L22T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_D1 L1T_D1 L2C_A0 L2T_A0
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE
CS1 D7 VREF_TL_09 A17
INIT
DOUT VREF_TL_10 A16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TDO -- -- --
CFG_IRQ/MPI_IRQ
PRD_DATA PRD_CFG
PPRGRM
PRD_DATA PRD_CFG
PPRGRM
PRD_DATA PRD_CFG
PPRGRM
PDONE PCFG_MPI_IRQ PCCLK PT21D PT21C PT20D PT20C
PDONE PCFG_MPI_IRQ PCCLK PT28D PT28C PT27D PT27C
PDONE PCFG_MPI_IRQ PCCLK PT35D PT35C PT34D PT34C
-- -- -- VREF_TC_01 --
90
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball C11 D12 B11 A11 C12 D13 B12 C13 D14 A13 C14 B14 A14 C15 B15 A15 D16 B16 A17 B17 C17 A18 B18 C18 A19 D18 M31 T1 T31 Y1 Y31 C16 B13 L4 R28 R4 R4 U28 J1 K3 H2 J3 K4 J2 G3 VDDIO VREF Bank Group 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 5 5 6 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 General-Purpose User I/O OR4E2 PT20B PT20A PT19D PT19C PT19B PT19A PT18D PT18C PT18B PT18A PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT13B PT13A PT12D PT12C PT12B PT12A VSS VSS VSS VSS VSS VDDIO_TC VDDIO_TC VDD15 VDD15 VDD15 VDD15 VDD15 PR8D PR8C PR7D PR7C PR7B PR7A PR6D OR4E4 PT27B PT27A PT26D PT26C PT26B PT26A PT25D PT25C PT24D PT24C PT23D PT23C PT21D PT21C PT19D PT19C PT18D PT18C PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C VSS VSS VSS VSS VSS VDDIO_TC VDDIO_TC VDD15 VDD15 VDD15 VDD15 VDD15 PR11D PR11C PR9D PR9C PR10D PR10C PR7D OR4E6 PT33D PT33C PT32D PT32C PT31D PT31C PT30D PT30C PT29D PT29C PT28D PT28C PT26D PT26C PT24D PT24C PT23D PT23C PT22D PT22C PT21D PT21C PT20D PT20C PT19D PT19C VSS VSS VSS VSS VSS VDDIO_TC VDDIO_TC VDD15 VDD15 VDD15 VDD15 VDD15 PR13D PR13C PR11D PR11C PR12D PR12C PR9D Additional Function -- -- -- VREF_TC_02 -- -- -- -- -- VREF_TC_03 -- -- -- -- -- VREF_TC_04 PTCK1C PTCK1T PTCK0C PTCK0T VREF_TC_05 -- -- -- -- VREF_TC_06 -- -- -- -- -- -- -- -- -- -- -- -- VREF_TR_01 -- -- -- -- -- -- Pair Differential
L3C_D0 L3T_D0 L4C_A0 L4T_A0 L5C_D0 L5T_D0 L6C_D0 L6T_D0 L7C_D2 L7T_D2 L8C_A0 L8T_A0 L9C_D1 L9T_D1 L10C_A0 L10T_A0 L11C_A1 L11T_A1 L12C_A0 L12T_A0 L13C_D1 L13T_D1 L14C_A0 L14T_A0 L15C_D2 L15T_D2 -- -- -- -- -- -- -- -- -- -- -- -- L1C_D1 L1T_D1 L3C_D0 L3T_D0 L2C_D1 L2T_D1 L5C_A0
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
Lucent Technologies Inc.
91
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball G2 J4 H3 F1 H4 F3 F2 F4 E3 E2 E1 D2 D1 B4 A4 D6 C5 B5 A5 C6 B6 A6 D8 C7 B7 D9 C8 B8 C9 D10 B9 C2 C30 C31 H1 H31 M1 D3 G1 A7 E4 D5 D4 D7 VDDIO VREF Bank Group 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 4 4 5 5 5 5 6 6 6 6 7 7 7 7 7 7 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- General-Purpose User I/O OR4E2 PR6C PR6B PR6A PR5B PR5A PR5D PR5C PR4D PR4C PR4B PR4A PR3D PR3C PT27D PT27C PT26D PT26C PT26B PT26A PT25D PT25C PT25B PT25A PT24D PT24C PT24B PT24A PT23D PT23C PT22D PT22C VSS VSS VSS VSS VSS VSS VDDIO_TR VDDIO_TR VDDIO_TR VDD33 VDD33 VDD15 VDD15 OR4E4 PR7C PR8D PR8C PR6B PR6A PR6D PR6C PR4D PR4C PR5D PR5C PR3D PR3C PT37D PT37C PT36D PT36C PT35B PT35A PT34D PT34C PT34B PT34A PT33D PT33C PT32D PT32C PT31D PT31C PT29D PT29C VSS VSS VSS VSS VSS VSS VDDIO_TR VDDIO_TR VDDIO_TR VDD33 VDD33 VDD15 VDD15 OR4E6 PR9C PR10D PR10C PR8D PR8C PR7D PR7C PR5D PR5C PR6D PR6C PR3D PR3C PT47D PT47C PT45D PT45C PT43D PT43C PT42D PT42C PT41D PT41C PT40D PT40C PT39D PT39C PT38D PT38C PT36D PT36C VSS VSS VSS VSS VSS VSS VDDIO_TR VDDIO_TR VDDIO_TR VDD33 VDD33 VDD15 VDD15 Additional Function VREF_TR_02 -- -- -- -- VREF_TR_03 -- -- -- -- -- PLL_CK3C PLL_CK3T PLL_CK2C PLL_CK2T VREF_TR_05 -- -- -- VREF_TR_06 -- -- -- -- VREF_TR_07 -- -- -- VREF_TR_08 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pair Differential
L5T_A0 L4C_D0 L4T_D0 L6C_D2 L6T_D2 L7C_A0 L7T_A0 L9C_D0 L9T_D0 L8C_A0 L8T_A0 L10C_A0 L10T_A0 L11C_A0 L11T_A0 L12C_D0 L12T_D0 L13C_A0 L13T_A0 L14C_A0 L14T_A0 L15C_D2 L15T_D2 L16C_A0 L16T_A0 L17C_D0 L17T_D0 L18C_D0 L18T_D0 L19C_D1 L19T_D1 -- -- -- -- -- -- -- -- -- -- -- -- --
TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- --
92
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball G28 G4 L28 C4 AB1 AB2 Y4 AA3 Y2 W4 AA1 AA2 W2 W3 W1 V4 V2 V3 U3 V1 T3 U1 R2 R1 T2 T4 P1 R3 P3 P2 P4 N1 M2 N3 L2 L1 M3 N4 K2 K1 L3 M4 B1 B29 VDDIO VREF Bank Group 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- -- 1 1 1 1 2 2 2 2 2 2 3 3 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 7 8 8 8 8 -- -- General-Purpose User I/O OR4E2 VDD15 VDD15 VDD15 PLL_VF PR20D PR20C PR19D PR19C PR18D PR18C PR18B PR18A PR17B PR17A PR17D PR17C PR16D PR16C PR15B PR15A PR15D PR15C PR14D PR14C PR14B PR14A PR13B PR13A PR13D PR13C PR12B PR12A PR12D PR12C PR11D PR11C PR11B PR11A PR9D PR9C PR10D PR10C VSS VSS OR4E4 VDD15 VDD15 VDD15 PLL_VF PR29D PR29C PR28D PR28C PR26B PR26A PR27B PR27A PR25B PR25A PR25D PR25C PR23D PR23C PR22D PR22C PR21D PR21C PR19D PR19C PR20D PR20C PR18D PR18C PR17D PR17C PR16D PR16C PR15D PR15C PR14D PR14C PR14B PR14A PR12D PR12C PR13D PR13C VSS VSS OR4E6 VDD15 VDD15 VDD15 PLL_VF PR35D PR35C PR33D PR33C PR31D PR31C PR32D PR32C PR30D PR30C PR29D PR29C PR27D PR27C PR26D PR26C PR25D PR25C PR23D PR23C PR24D PR24C PR22D PR22C PR21D PR21C PR20D PR20C PR19D PR19C PR17D PR17C PR18D PR18C PR14D PR14C PR15D PR15C VSS VSS Additional Function -- -- -- -- -- -- -- VREF_CR_01 VREF_CR_02 -- -- -- -- -- VREF_CR_03 -- PRCK1C PRCK1T VREF_CR_04 -- -- -- -- VREF_CR_05 PRCK0C PRCK0T -- -- VREF_CR_06 -- -- -- -- -- -- VREF_CR_07 -- -- -- VREF_CR_08 -- -- -- -- Pair Differential
-- -- -- -- L1C_A0 L1T_A0 L2C_D0 L2T_D0 L4C_D1 L4T_D1 L3C_A0 L3T_A0 L5C_A0 L5T_A0 L6C_D2 L6T_D2 L7C_A0 L7T_A0 L8C_D1 L8T_D1 L9C_D1 L9T_D1 L11C_A0 L11T_A0 L10C_A1 L10T_A1 L12C_D1 L12T_D1 L13C_A0 L13T_A0 L14C_D2 L14T_D2 L15C_D0 L15T_D0 L17C_A0 L17T_A0 L16C_D0 L16T_D0 L19C_A0 L19T_A0 L18C_D0 L18T_D0 -- --
-- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- --
Lucent Technologies Inc.
93
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball B3 B31 C1 N2 U2 Y3 D15 D17 D21 D25 D28 AJ8 AK8 AJ9 AH10 AK9 AL9 AL6 AH8 AJ7 AK7 AL7 AJ5 AK5 AL5 AJ6 AK6 AJ4 AK4 AL4 AH6 AH1 AH2 AG3 AF4 AG1 AG2 AE3 AD4 AF2 AF3 AD3 AC4 AE1 AE2 VDDIO VREF Bank Group 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 6 6 7 7 7 7 General-Purpose User I/O OR4E2 VSS VSS VSS VDDIO_CR VDDIO_CR VDDIO_CR VDD15 VDD15 VDD15 VDD15 VDD15 PB23B PB23A PB22D PB22C PB22B PB22A PB24C PB24B PB24A PB23D PB23C PB26D PB26C PB25D PB25C PB25A PB27D PB27C PB27B PB27A PR26B PR26A PR25B PR25A PR25D PR25C PR24D PR24C PR24B PR24A PR23D PR23C PR23B PR23A OR4E4 VSS VSS VSS VDDIO_CR VDDIO_CR VDDIO_CR VDD15 VDD15 VDD15 VDD15 VDD15 PB32D PB32C PB31D PB31C PB30D PB30C PB34C PB34B PB34A PB33D PB33C PB36D PB36C PB35D PB35C PB35A PB37D PB37C PB37B PB37A PR38B PR38A PR37D PR37C PR36D PR36C PR35D PR35C PR35B PR35A PR33D PR33C PR34D PR34C OR4E6 VSS VSS VSS VDDIO_CR VDDIO_CR VDDIO_CR VDD15 VDD15 VDD15 VDD15 VDD15 PB39D PB39C PB38D PB38C PB37D PB37C PB42C PB41D PB41C PB40D PB40C PB45D PB45C PB44D PB44C PB43A PB47D PB47C PB46D PB46C PR46D PR46C PR44D PR44C PR43D PR43C PR41D PR41C PR42D PR42C PR39D PR39C PR40D PR40C Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_BR_01 -- -- -- -- -- VREF_BR_02 -- -- -- VREF_BR_03 -- -- PLL_CK5C PLL_CK5T VREF_BR_04 -- PLL_CK4C PLL_CK4T -- VREF_BR_05 -- -- -- VREF_BR_06 -- -- VREF_BR_07 -- -- -- Pair Differential
-- -- -- -- -- -- -- -- -- -- -- L3C_A0 L3T_A0 L2C_D0 L2T_D0 L1C_A0 L1T_A0 -- L5C_D0 L5T_D0 L4C_A0 L4T_A0 L7C_A0 L7T_A0 L6C_D1 L6T_D1 -- L9C_A0 L9T_A0 L8C_D2 L8T_D2 L10C_A0 L10T_A0 L11C_D0 L11T_D0 L12C_A0 L12T_A0 L14C_D0 L14T_D0 L13C_A0 L13T_A0 L16C_D0 L16T_D0 L15C_A0 L15T_A0
-- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE
94
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball AC3 AD2 AC2 AB4 AB3 AC1 AL20 AL24 AL29 AL3 AL30 AL8 AF1 AH3 AH9 AG4 AH5 B2 B30 C29 C3 D11 AK17 AJ17 AL18 AK18 AL15 AK16 AJ16 AL17 AL13 AJ14 AK14 AL14 AJ15 AK15 AL11 AJ12 AH13 AK12 AK13 AH14 AL10 AJ11 AH12 VDDIO VREF Bank Group 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 7 7 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 General-Purpose User I/O OR4E2 PR22B PR22A PR22D PR22C PR21D PR21C VSS VSS VSS VSS VSS VSS VDDIO_BR VDDIO_BR VDDIO_BR VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PB13D PB13C PB13B PB13A PB15D PB15C PB14D PB14C PB17D PB17C PB17B PB17A PB16D PB16C PB19B PB19A PB18D PB18C PB18B PB18A PB20D PB20C PB19D OR4E4 PR32D PR32C PR31D PR31C PR30D PR30C VSS VSS VSS VSS VSS VSS VDDIO_BR VDDIO_BR VDDIO_BR VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PB18D PB18C PB17D PB17C PB20D PB20C PB19D PB19C PB23D PB23C PB22D PB22C PB21D PB21C PB26B PB26A PB25D PB25C PB24D PB24C PB27D PB27C PB26D OR4E6 PR38D PR38C PR37D PR37C PR36D PR36C VSS VSS VSS VSS VSS VSS VDDIO_BR VDDIO_BR VDDIO_BR VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PB22D PB22C PB21D PB21C PB24D PB24C PB23D PB23C PB28D PB28C PB27D PB27C PB26D PB26C PB31D PB31C PB30D PB30C PB29D PB29C PB34D PB34C PB32D Additional Function -- -- VREF_BR_08 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_BC_01 -- -- -- VREF_BC_02 PBCK0C PBCK0T PBCK1C PBCK1T -- -- VREF_BC_03 -- -- -- VREF_BC_04 -- -- -- -- -- VREF_BC_05 Pair Differential
L17C_D0 L17T_D0 L18C_D1 L18T_D1 L19C_D1 L19T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L2C_A0 L2T_A0 L1C_A0 L1T_A0 L4C_D0 L4T_D0 L3C_D1 L3T_D1 L7C_D1 L7T_D1 L6C_A0 L6T_A0 L5C_A0 L5T_A0 L10C_D1 L10T_D1 L9C_D1 L9T_D1 L8C_A0 L8T_A0 L12C_D1 L12T_D1 L11C_D1
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
Lucent Technologies Inc.
95
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball AK11 AJ10 AK10 AK3 AK31 AL12 AL16 AL2 AJ13 AH16 AJ3 AK2 AK30 AL1 AL31 AC29 AD30 AD29 AC28 AE31 AE30 AF30 AF29 AD28 AF31 AG29 AF28 AG31 AG30 AJ27 AH26 AL28 AK28 AJ28 AH24 AL26 AK26 AJ26 AL27 AK27 AJ23 AK24 AJ24 AH23 AL25 VDDIO VREF Bank Group 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 6 6 -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 2 2 3 3 3 3 4 4 4 4 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 General-Purpose User I/O OR4E2 PB19C PB21B PB21A VSS VSS VSS VSS VSS VDDIO_BC VDDIO_BC VDD15 VDD15 VDD15 VDD15 VDD15 PL22D PL22C PL22B PL22A PL23D PL23C PL25D PL25C PL24D PL24C PL27D PL27C PL26D PL26C PB3D PB3C PB2D PB2C PB2A PB5B PB5A PB4D PB4C PB4B PB4A PB6D PB6C PB6B PB6A PB5D OR4E4 PB26C PB28D PB28C VSS VSS VSS VSS VSS VDDIO_BC VDDIO_BC VDD15 VDD15 VDD15 VDD15 VDD15 PL32D PL32C PL33D PL33C PL34D PL34C PL36B PL36A PL35B PL35A PL39D PL39C PL37B PL37A PB4B PB4A PB2D PB2C PB2A PB6B PB6A PB5D PB5C PB4D PB4C PB8D PB8C PB7D PB7C PB6D OR4E6 PB32C PB35D PB35C VSS VSS VSS VSS VSS VDDIO_BC VDDIO_BC VDD15 VDD15 VDD15 VDD15 VDD15 PL38D PL38C PL39D PL39C PL40D PL40C PL44D PL44C PL42D PL42C PL47D PL47C PL45D PL45C PB4D PB4C PB2D PB2C PB2A PB7D PB7C PB6D PB6C PB5D PB5C PB10D PB10C PB9D PB9C PB8D Additional Function -- VREF_BC_06 -- -- -- -- -- -- -- -- -- -- -- -- -- D8 VREF_BL_01 D9 D10 -- VREF_BL_02 VREF_BL_03 D13 D11 D12 PLL_CK7C PLL_CK7T -- VREF_BL_04 DP3 VREF_BL_05 PLL_CK6C PLL_CK6T DP2 -- -- D14 VREF_BL_06 -- -- D19 VREF_BL_07 D18 D17 D16 Pair Differential
L11T_D1 L13C_A0 L13T_A0 -- -- -- -- -- -- -- -- -- -- -- -- L1C_D0 L1T_D0 L2C_D0 L2T_D0 L3C_A0 L3T_A0 L5C_A0 L5T_A0 L4C_D2 L4T_D2 L7C_D1 L7T_D1 L6C_A0 L6T_A0 L9C_D0 L9T_D0 L8C_A0 L8T_A0 -- L12C_D2 L12T_D2 L11C_A0 L11T_A0 L10C_A0 L10T_A0 L15C_D0 L15T_D0 L14C_D0 L14T_D0 L13C_A0
TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT
96
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 45.OR4E6 432-Pin EBGA (continued)
432 BGA Ball AK25 AJ22 AL23 AK23 AH22 AH20 AJ21 AL22 AK22 AJ19 AK20 AJ20 AL21 AK21 AJ18 AL19 AH18 AK19 AJ1 AJ2 AJ30 AJ31 AK1 AK29 AH19 AJ25 AH30 AE29 AH27 AG28 AH25 AH28 AH4 AH7 AJ29 AH31 AH29 M29 N28 L30 L31 M30 N29 N30 VDDIO VREF Bank Group 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 10 11 11 11 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 2 2 2 General-Purpose User I/O OR4E2 PB5C PB7D PB7C PB7B PB7A PB9D PB9C PB8D PB8C PB11D PB11C PB11B PB10D PB10C PB12D PB12C PB12B PB12A VSS VSS VSS VSS VSS VSS VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PTEMP LVDS_R PL9D PL9C PL8D PL8C PL9B PL10D PL10C OR4E4 PB6C PB10D PB10C PB9D PB9C PB12D PB12C PB11D PB11C PB14D PB14C PB14B PB13D PB13C PB16D PB16C PB15D PB15C VSS VSS VSS VSS VSS VSS VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PTEMP LVDS_R PL13D PL13C PL12D PL12C PL13B PL14D PL14C OR4E6 PB8C PB12D PB12C PB11D PB11C PB14D PB14C PB13D PB13C PB18D PB18C PB17D PB16D PB16C PB20D PB20C PB19D PB19C VSS VSS VSS VSS VSS VSS VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 PTEMP LVDS_R PL16D PL16C PL14D PL14C PL17D PL18D PL18C Additional Function D15 D22 VREF_BL_08 D21 D20 D25 VREF_BL_09 D24 D23 D28 VREF_BL_10 -- D27 D26 D31 VREF_BL_11 D30 D29 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_7_01 D4 A15 A14 -- RDY/BUSY/RCLK VREF_7_02 L20C_A0 L20T_A0 L23C_D1 L23T_D1 L22C_D1 L22T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L2C_D0 L2T_D0 L1C_A0 L1T_A0 -- L3C_A0 L3T_A0 Pair Differential
L13T_A0 L17C_D1 L17T_D1 L16C_D1 L16T_D1 L19C_D0 L19T_D0 L18C_A0 L18T_A0 L21C_D0 L21T_D0
TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT COMPLEMENT TRUE
Lucent Technologies Inc.
97
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 45. OR4E6 432-Pin EBGA (continued)
432 BGA Ball N31 P29 P30 P31 R29 R30 T28 T30 R31 T29 V31 V30 U30 U29 W29 Y30 V29 W31 V28 W30 AA31 AA30 Y29 AB29 AC31 AC30 AB28 Y28 AA29 AB31 AB30 A3 A30 A8 AD1 AD31 W28 U31 P28 AE4 AH11 AH15 AH17 AH21 VDDIO VREF Bank Group 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 6 6 7 7 7 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- General-Purpose User I/O OR4E2 PL10B PL10A PL11D PL11C PL11B PL11A PL14D PL14C PL13D PL13C PL16D PL16C PL15D PL15C PL18D PL18C PL17D PL17C PL17B PL17A PL19D PL19C PL18B PL21D PL21C PL21B PL21A PL20D PL20C PL20B PL20A VSS VSS VSS VSS VSS VDDIO_CL VDDIO_CL VDDIO_CL VDD15 VDD15 VDD15 VDD15 VDD15 OR4E4 PL15D PL15C PL16D PL16C PL17D PL17C PL20D PL20C PL19D PL19C PL22D PL22C PL21D PL21C PL26D PL26C PL24D PL24C PL25D PL25C PL27D PL27C PL26B PL30D PL30C PL31D PL31C PL28D PL28C PL29D PL29C VSS VSS VSS VSS VSS VDDIO_CL VDDIO_CL VDDIO_CL VDD15 VDD15 VDD15 VDD15 VDD15 OR4E6 PL19D PL19C PL20D PL20C PL21D PL21C PL24D PL24C PL23D PL23C PL26D PL26C PL25D PL25C PL30D PL30C PL28D PL28C PL29D PL29C PL32D PL32C PL31D PL36D PL36C PL37D PL37C PL34D PL34C PL35D PL35C VSS VSS VSS VSS VSS VDDIO_CL VDDIO_CL VDDIO_CL VDD15 VDD15 VDD15 VDD15 VDD15 Additional Function A13 A12 -- -- A11 VREF_7_03 PLCK0C PLCK0T
RD/MPI_STRB
Pair
Differential
L4C_D1 L4T_D1 L5C_A0 L5T_A0 L6C_A0 L6T_A0 L8C_A1 L8T_A1 L7C_D1 L7T_D1 L10C_A0 L10T_A0 L9C_A0 L9T_A0 L13C_D0 L13T_D0 L11C_D1 L11T_D1 L12C_D1 L12T_D1 L14C_A0 L14T_A0 -- L17C_D1 L17T_D1 L18C_D1 L18T_D1 L15C_D0 L15T_D0 L16C_A0 L16T_A0 -- -- -- -- -- -- -- -- -- -- -- -- --
COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- --
VREF_7_04 A8 VREF_7_05 A10 A9 A6 A5 PLCK1C PLCK1T VREF_7_06 A7
WR/MPI_RW
VREF_7_07 -- A1 A0 DP0 DP1 A4 VREF_7_08 A3 A2 -- -- -- -- -- -- -- -- -- -- -- -- --
98
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:
s s s s
_A1 indicates one ball between pairs. _A2 indicates two balls between pairs. _D0 indicates balls are diagonally adjacent. _D1 indicates diagonally adjacent separated by one physical ball.
VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank). Table 46. 680-Pin PBGAM Pinout
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function MPI_RTRY MPI_ACK Pair Differential
E16 D14 C14 D13 A12 B12 E15 B11 C11 E14 D12 D11 A10 B10 C10 C9 D10 E13 B9 A9 D9 A8 B8 E12 C8 D8 E11
TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL
1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 4 4 4 5
PT13D PT13C PT13B PT13A PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A PT10D PT10C PT10A PT9D PT9C PT9A PT8D PT8C PT7D PT7C PT6D PT6C PT6B PT6A PT5D
PT18D PT18C PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT12D PT12C PT12A PT11D PT11C PT11A PT10D PT10C PT9D PT9C PT8D PT8C PT7D PT7C PT6D
L1C_D1 COMPLEMENT L1T_D1 L2T_D0 L3C_A0 L3T_A0 L4T_D3 TRUE TRUE COMPLEMENT TRUE TRUE L2C_D0 COMPLEMENT
-- VREF_TL_01 M0 M1 MPI_CLK A21/ MPI_BURST M2 M3 VREF_TL_02
MPI_TEA
L4C_D3 COMPLEMENT
L5C_D2 COMPLEMENT L5T_D2 L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- L8T_D0 -- L9C_A0 L9T_A0 TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE 99
-- -- -- VREF_TL_03 -- -- D0 TMS
L8C_D0 COMPLEMENT
A20/MPI_BDIP L10C_D2 COMPLEMENT A19/MPI_TSZ1 L10T_D2 D3 VREF_TL_04 -- D1 L11T_D3 L12T_A0 A18/MPI_TSZ0 L11C_D3 COMPLEMENT L12C_A0 COMPLEMENT L13C_D3 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
A7 A6 B7 C7 D7 E10 A5 B6 E9 A4 B5 D6 C6 C5 E8 D1 F4 F3 G4 E2 H5 E1 F2 J5 F1 H4 G3 H3 G2 K5 G1 J4 L5 J3 100
TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL
5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 10
PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A PL2D PL2C PL3D PL3C PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A PL6D PL6C PL7D PL7C PL8D PL8C PL9D
PT6C PT5D PT5C PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A PL2D PL2C PL3D PL3C PL4D PL4C PL5D PL5C PL6D PL6C PL7D PL7C PL8D PL8C PL9D PL9C PL10D PL10C PL11D
D2 -- VREF_TL_05 TDI TCK -- -- -- VREF_TL_06 -- -- PLL_CK1C/ PPLL PLL_CK1T/ PPLL -- -- PLL_CK0C/ HPPLL PLL_CK0T/ HPPLL -- VREF_TL_07 D5 D6 -- VREF_TL_08 HDC
LDC
L13T_D3 L14T_D0 L15T_A0 L16T_D4 L17T_D2 L18T_D0
TRUE TRUE TRUE TRUE TRUE TRUE
L14C_D0 COMPLEMENT L15C_A0 COMPLEMENT L16C_D4 COMPLEMENT L17C_D2 COMPLEMENT L18C_D0 COMPLEMENT L19C_A0 COMPLEMENT L19T_A0 TRUE
L20C_D1 COMPLEMENT L20T_D1 TRUE L21C_D2 COMPLEMENT L21T_D2 TRUE
L22C_D0 COMPLEMENT L22T_D0 L23T_D2 L24T_D0 L25T_D3 L26T_D0 L27T_D0 L28T_D3 L29T_D1 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE L23C_D2 COMPLEMENT L24C_D0 COMPLEMENT L25C_D3 COMPLEMENT L26C_D0 COMPLEMENT L27C_D0 COMPLEMENT L28C_D3 COMPLEMENT L29C_D1 COMPLEMENT L30C_D0 COMPLEMENT Lucent Technologies Inc.
-- -- -- D7 VREF_TL_09 A17
CS0
CS1 --
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
H2 K4 H1 J2 J1 K3 M5 F5 E4 E3 D2 G5 E7 E6 B4 D5 A1 A2 A18 A33 A34 B1 B2 B33 B34 C3 C13 N16 N17 N18 N19 P16 P17 A3 B3 C1 C2
TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL
10 10 10 10 10 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PL9C PL9A PL10D PL10C PL11D PL11C PL11A VDD33 PRD_DATA
PRESET PRD_CFG PPRGRM
PL11C PL11A PL12D PL12C PL13D PL13C PL13A VDD33 PRD_DATA
PRESET PRD_CFG PPRGRM
-- --
INIT
L30T_D0 -- L31T_D0 L32T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
TRUE TRUE TRUE TRUE TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 101
L31C_D0 COMPLEMENT L32C_D1 COMPLEMENT
DOUT VREF_TL_10 A16 -- -- -- -- -- --
CFG_IRQ/ MPI_IRQ
PCFG_MPI_IRQ PCCLK PDONE VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_TL VDDIO_TL VDDIO_TL VDDIO_TL
PCFG_MPI_IRQ PCCLK PDONE VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_TL VDDIO_TL VDDIO_TL VDDIO_TL
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
C4 D3 E5 C25 E24 D24 A25 D23 B25 C24 E23 B24 D22 E22 D21 B23 B22 A23 C21 E21 D20 A22 E20 A21 B21 D19 B20 A20 B19 C19 E19 D18 B18 C18 B17 C17 D17 A16 102
TL TL TL TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC
-- -- -- 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 5 5 5 5
VDDIO_TL VDDIO_TL VDDIO_TL PT28D PT28C PT28A PT28B PT27D PT27C PT27B PT27A PT26D PT26C PT26B PT26A PT25D PT25C PT24D PT24C PT24A PT23D PT23C PT23A PT22D PT22C PT22A PT21D PT21C PT20D PT20C PT19D PT19C PT19A PT19B PT18D PT18C PT18A PT18B
VDDIO_TL VDDIO_TL VDDIO_TL PT35D PT35C PT35A PT35B PT34D PT34C PT33D PT33C PT32D PT32C PT31D PT31C PT30D PT30C PT29D PT29C PT29A PT28D PT28C PT28A PT27D PT27C PT27A PT26D PT26C PT25D PT25C PT24D PT24C PT24A PT24B PT23D PT23C PT23A PT23B
-- -- -- -- -- -- -- VREF_TC_01 -- -- -- -- VREF_TC_02 -- -- -- -- -- VREF_TC_03 -- -- -- -- -- -- -- -- -- -- -- -- VREF_TC_04 -- -- PTCK1C PTCK1T
-- -- -- L1T_D1 L2T_D2
-- -- -- TRUE TRUE
L1C_D1 COMPLEMENT
L2C_D2 COMPLEMENT L3C_D1 COMPLEMENT L3T_D1 L4T_D1 L5T_D1 L6T_D0 L7C_A0 L7T_A0 L8T_D1 -- L9T_D2 -- L10T_A0 -- L11T_A0 L12T_A0 L13T_D0 L14T_A0 TRUE TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE L4C_D1 COMPLEMENT L5C_D1 COMPLEMENT L6C_D0 COMPLEMENT
L8C_D1 COMPLEMENT
L9C_D2 COMPLEMENT
L10C_A0 COMPLEMENT
L11C_A0 COMPLEMENT L12C_A0 COMPLEMENT L13C_D0 COMPLEMENT
L14C_A0 COMPLEMENT L15C_D0 COMPLEMENT L15T_D0 L16T_D2 TRUE TRUE
L16C_D2 COMPLEMENT Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
B16 C16 D16 E18 A15 B15 D15 A14 B14 E17 A13 B13 C22 C32 D4 D31 N3 N13 N14 N15 N20 N21 N22 P18 P19 R16 R17 R18 R19 A11 A17 A19 A24 C12 C15 C20 C23 J34
TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TR
5 5 5 5 5 5 6 6 6 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1
PT17D PT17C PT17A PT16D PT16C PT16A PT15D PT15C PT15A PT14D PT14C PT14A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC PR11B
PT22D PT22C PT22A PT21D PT21C PT21A PT20D PT20C PT20A PT19D PT19C PT19A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC VDDIO_TC PR13B
PTCK0C PTCK0T -- VREF_TC_05 -- -- -- -- -- -- VREF_TC_06 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
L17C_A0 COMPLEMENT L17T_A0 -- L18T_D3 -- L19T_D2 -- L20T_D3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_A0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT 103
L18C_D3 COMPLEMENT
L19C_D2 COMPLEMENT
L20C_D3 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
H34 J33 J31 J32 G34 M30 H33 H32 L30 H31 G33 F34 F33 G32 K30 G31 E34 J30 D34 F32 F31 E33 D33 H30 E32 E31
TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR
1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4
PR11A PR11C PR11D PR10C PR10D PR9A PR9C PR9D PR8A PR8C PR8D PR7A PR7C PR7D PR6A PR6B PR6C PR6D PR5A PR5C PR5D PR4C PR4D PR3A PR3B PR3C
PR13A PR13C PR13D PR12C PR12D PR11A PR11C PR11D PR10A PR10C PR10D PR9A PR9C PR9D PR8C PR8D PR7C PR7D PR6A PR6C PR6D PR5C PR5D PR4C PR4D PR3C
-- -- VREF_TR_01 -- -- -- -- -- -- -- -- -- VREF_TR_02 -- -- -- -- VREF_TR_03 -- -- -- -- -- -- VREF_TR_04 PLL_CK3T/ PLL1(1.554/ 2.048 MHz) PLL_CK3C/ PLL1(1.554/ 2.048 MHz) PLL_CK2C/ PPLL PLL_CK2T/ PPLL -- -- VREF_TR_05 --
L1T_A0 L2T_A1 L2C_A1 L3T_D1 -- L4T_A0 L4C_A0 -- L5T_D1 -- L6T_D0 L7T_D2 L8T_D2 -- L9T_A0 L9C_A0 L10T_A0 L11T_D2 L12T_A0
TRUE TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE
L3C_D1 COMPLEMENT
L5C_D1 COMPLEMENT
L6C_D0 COMPLEMENT L7C_D2 COMPLEMENT L8C_D2 COMPLEMENT
L10C_A0 COMPLEMENT L11C_D2 COMPLEMENT
G30
TR
4
PR3D
PR3D
L12C_A0 COMPLEMENT
C30 B31 E28 B30 D29 A31 104
TR TR TR TR TR TR
5 5 5 5 5 5
PT37D PT37C PT37B PT37A PT36D PT36C
PT47D PT47C PT46D PT46C PT45D PT45C
L13C_D0 COMPLEMENT L13T_D0 TRUE
L14C_D2 COMPLEMENT L14T_D2 L15T_D2 TRUE TRUE L15C_D2 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
D28 B29 E27 C29 A30 E26 A29 D27 C28 C27 B28 E25 A28 D26 C26 B27 D25 A27 A26 B26 F30 E29 D30 N32 P13 P14 P15 P20 P21 P22 R13 R14 R15 R20 T13 T14 T15
TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR
6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PT35D PT35C PT35B PT35A PT34D PT34C PT34B PT34A PT33D PT33C PT32D PT32C PT31D PT31C PT30D PT30A PT29D PT29C PT29A PT29B VDD33 VDD33 PLL_VF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15
PT44D PT44C PT43D PT43C PT42D PT42C PT41D PT41C PT40D PT40C PT39D PT39C PT38D PT38C PT37D PT37A PT36D PT36C PT36A PT36B VDD33 VDD33 PLL_VF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15
-- -- -- -- VREF_TR_06 -- -- -- -- VREF_TR_07 -- -- -- VREF_TR_08 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
L16C_D1 COMPLEMENT L16T_D1 L17T_D1 L18T_D3 L19T_D2 L20T_A0 L21T_D2 L22T_D2 -- -- L23T_D2 L24T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE TRUE TRUE TRUE TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 105 L17C_D1 COMPLEMENT L18C_D3 COMPLEMENT L19C_D2 COMPLEMENT L20C_A0 COMPLEMENT L21C_D2 COMPLEMENT L22C_D2 COMPLEMENT
L23C_D2 COMPLEMENT
L24C_A0 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
T20 T21 T22 A32 B32 C31 C33 C34 D32 E30 AE32 AC30 AD31 AE33 AC31 AE34 AD32 AB30 AD33 AB31 AA30 AA31 AC33 AB33 AC34 AA32 Y30 Y31 AB34 W30 AA34 AA33 W31 Y33 Y34 W33 W32 106
TR TR TR TR TR TR TR TR TR TR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR
-- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4
VDD15 VDD15 VDD15 VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR PR29A PR29B PR28A PR29C PR29D PR28B PR28C PR28D PR27D PR27A PR27B PR27C PR26A PR26B PR26C PR25A PR25B PR24B PR25C PR25D PR24A PR24C PR24D PR23A PR23C PR23D PR22A
VDD15 VDD15 VDD15 VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR VDDIO_TR PR35C PR35D PR34A PR34C PR34D PR33B PR33C PR33D PR32B PR32C PR32D PR31A PR31C PR31D PR30A PR30C PR30D PR29B PR29C PR29D PR28A PR28C PR28D PR27A PR27C PR27D PR26A
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_CR_01 -- -- -- -- -- -- VREF_CR_02 -- -- -- -- -- VREF_CR_03 -- -- -- -- PRCK1T PRCK1C --
-- -- -- -- -- -- -- -- -- -- L1T_D1 -- L2T_D1 -- L3T_D1 -- L4T_D0 -- L5T_A0 L5C_A0 -- L6T_D1 -- L7T_D3 -- L8T_D1 -- L9T_D0 --
-- -- -- -- -- -- -- -- -- -- TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE TRUE TRUE
L1C_D1 COMPLEMENT
L2C_D1 COMPLEMENT
L3C_D1 COMPLEMENT
L4C_D0 COMPLEMENT
L6C_D1 COMPLEMENT
L7C_D3 COMPLEMENT
L8C_D1 COMPLEMENT
L9C_D0 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
V30 V31 V33 V32 U33 U32 T34 U31 T33 T32 T31 U30 R31 R34 R33 P34 P32 T30 P31 P33 R30 N33 N31 N34 M31 M33 P30 M34 L32 L31 L33 K34 K33 K32 N30 K31 R21
CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR
4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 --
PR22C PR22D PR21C PR21D PR20A PR20B PR20C PR20D PR19A PR19C PR19D PR18A PR18C PR18D PR17A PR17C PR17D PR16A PR16C PR16D PR16B PR15C PR15D PR15B PR14A PR14B PR15A PR14C PR14D PR13B PR13A PR13C PR13D PR12A PR12C PR12D VSS
PR26C PR26D PR25C PR25D PR24A PR24B PR24C PR24D PR23A PR23C PR23D PR22A PR22C PR22D PR21A PR21C PR21D PR20A PR20C PR20D PR19B PR19C PR19D PR18B PR18C PR18D PR17A PR17C PR17D PR16D PR15A PR15C PR15D PR14A PR14C PR14D VSS
-- VREF_CR_04 -- -- -- -- PRCK0T PRCK0C -- VREF_CR_05 -- -- -- -- -- -- VREF_CR_06 -- -- -- -- -- -- -- -- -- -- VREF_CR_07 -- -- -- -- -- -- VREF_CR_08 -- --
L10T_A0 L11T_A0 L12T_A0 L13T_D2 -- L14T_A0 -- L15T_D1 -- L16T_A1 -- L17T_A1 -- L18T_A1 -- L19T_A1 -- L20T_D1 -- -- L21T_A0 -- L22T_D2 --
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE -- 107
L10C_A0 COMPLEMENT L11C_A0 COMPLEMENT L12C_A0 COMPLEMENT L13C_D2 COMPLEMENT
L14C_A0 COMPLEMENT
L15C_D1 COMPLEMENT
L16C_A1 COMPLEMENT
L17C_A1 COMPLEMENT
L18C_A1 COMPLEMENT
L19C_A1 COMPLEMENT
L20C_D1 COMPLEMENT
L21C_A0 COMPLEMENT
L22C_D2 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
R22 T16 T17 T18 T19 U16 U17 U18 U19 V1 U13 U14 U15 U20 U21 U22 L34 M32 R32 U34 W34 Y32 AC32 AD34 AM26 AP27 AN27 AK25 AL26 AM27 AK26 AP28 AN28 AL27 AL28 AK27 AM28 AN29 108
CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR CR BR BR BR BR BR BR BR BR BR BR BR BR BR BR
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 2 2 2 2 2 3 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR PB30A PB30C PB30D PB31C PB31D PB32C PB32D PB33C PB33D PB34A PB34B PB34C PB35A PB35B
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR VDDIO_CR PB37A PB37C PB37D PB38C PB38D PB39C PB39D PB40C PB40D PB41C PB41D PB42C PB43A PB43D
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_BR_01 -- -- -- -- VREF_BR_02 -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1T_A0 L1C_A0 L2T_D0 L3T_D1 L4T_A0 L4C_A0 L5T_A0 L5C_A0 -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT
L2C_D0 COMPLEMENT L3C_D1 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AK28 AM29 AP29 AL29 AP30 AN30 AK29 AM30 AL30 AP31 AJ30 AK32 AL33 AH30 AL34 AJ31 AJ32 AH31 AK33 AG30 AK34 AJ33 AF30 AJ34 AG31 AH32 AG32 AH33 AE30 AH34 AF31 AF32 AG33 AE31 AG34
BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR
3 3 3 3 3 3 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8
PB35C PB35D PB36B PB36A PB36C PB36D PB37A PB37B PB37C PB37D PR38A PR38B PR38C PR38D PR37C PR37D PR36C PR36D PR35A PR35B PR35C PR35D PR34A PR34C PR34D PR33A PR33C PR33D PR32A PR32C PR32D PR31A PR31C PR31D PR30A
PB44C PB44D PB45B PB45A PB45C PB45D PB46C PB46D PB47C PB47D PR46C PR46D PR45C PR45D PR44C PR44D PR43C PR43D PR42C PR42D PR41C PR41D PR40A PR40C PR40D PR39A PR39C PR39D PR38A PR38C PR38D PR37A PR37C PR37D PR36A
-- VREF_BR_03 -- -- -- -- -- VREF_BR_04 PLL_CK5T/ PPLL PLL_CK5C/ PPLL
PLL_CK4T/PLL2 (155.52 MHz)
L6T_D1 L7C_A2 L7T_A2 L8T_A0 L8C_A0 L9T_D1 L10T_D2
TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE TRUE
L6C_D1 COMPLEMENT
L9C_D1 COMPLEMENT
L10C_D2 COMPLEMENT L11T_D1 TRUE
PLL_CK4C/PLL2 L11C_D1 COMPLEMENT (155.52 MHz)
-- -- VREF_BR_05 -- -- -- -- -- VREF_BR_06 -- -- -- -- -- -- VREF_BR_07 -- -- -- -- -- VREF_BR_08 --
L12T_D2 L13T_D2 L14T_D0 L15T_D2 L16T_D0 -- L17T_D2 -- L18T_D0 -- L19T_D2 -- L20T_D1 --
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 109
L12C_D2 COMPLEMENT L13C_D2 COMPLEMENT L14C_D0 COMPLEMENT L15C_D2 COMPLEMENT L16C_D0 COMPLEMENT
L17C_D2 COMPLEMENT
L18C_D0 COMPLEMENT
L19C_D2 COMPLEMENT
L20C_D1 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AF33 AD30 AF34 AN31 AK31 V16 V17 V18 V19 V34 W16 W17 W18 W19 Y13 Y14 V13 V14 V15 V20 V21 V22 AK30 AL32 AM31 AM33 AM34 AN32 AP32 AN15 AN16 AK17 AL16 AM16 AP16 AN17 AL17 AM17 110
BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BC BC BC BC BC BC BC BC BC
8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 2 2
PR30B PR30C PR30D VDD33 VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR PB17A PB17C PB17D PB18A PB18C PB18D PB19A PB19B PB19C
PR36B PR36C PR36D VDD33 VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR VDDIO_BR PB21A PB21C PB21D PB22A PB22C PB22D PB23A PB23B PB23C
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_BC_01 -- -- -- PBCK0T
-- L21T_D3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1T_D2 -- L2T_A1 L2C_A1 L3T_A1 L3C_A1 L4T_A0
COMPLEMENT TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE
L21C_D3 COMPLEMENT
L1C_D2 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AM18 AN18 AL18 AL19 AK18 AM19 AN19 AP20 AN20 AL20 AP21 AN21 AK19 AM21 AL21 AK20 AP22 AN22 AK21 AL22 AL23 AK22 AN23 AP23 AK23 AN24 AM24 AL24 AP25 AN25 AK24 AP26 AN26 AL25 AM25 Y15 Y20 Y21
BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC
2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 -- -- --
PB19D PB20B PB20A PB20C PB20D PB21A PB21B PB21C PB21D PB22A PB22C PB22D PB23A PB23C PB23D PB24A PB24C PB24D PB25A PB25C PB25D PB26A PB26B PB26C PB26D PB27A PB27B PB27C PB27D PB28A PB28C PB28D PB29A PB29C PB29D VSS VSS VSS
PB23D PB24B PB24A PB24C PB24D PB25C PB25D PB26C PB26D PB27A PB27C PB27D PB28A PB28C PB28D PB29A PB29C PB29D PB30A PB30C PB30D PB31C PB31D PB32C PB32D PB33C PB33D PB34C PB34D PB35A PB35C PB35D PB36A PB36C PB36D VSS VSS VSS
PBCK0C -- -- VREF_BC_02 -- -- -- -- VREF_BC_03 -- -- -- -- PBCK1T PBCK1C -- -- -- -- -- VREF_BC_04 -- -- -- VREF_BC_05 -- -- -- -- -- -- VREF_BC_06 -- -- -- -- -- --
L4C_A0 L5C_A1 L5T_A1 L6T_D0 L7T_A0 L7C_A0 L8T_A0 L8C_A0 -- L9T_A0 L9C_A0 -- L10T_A0 -- L11T_A0 -- L12T_A0 L13T_D2 L14T_A3 L15T_A0 L16T_D2 -- L17T_D3 -- L18T_A0 -- -- --
COMPLEMENT COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE -- -- -- 111
L6C_D0 COMPLEMENT
L10C_A0 COMPLEMENT
L11C_A0 COMPLEMENT
L12C_A0 COMPLEMENT L13C_D2 COMPLEMENT L14C_A3 COMPLEMENT L15C_A0 COMPLEMENT L16T_D2 COMPLEMENT
L17C_D3 COMPLEMENT
L18C_A0 COMPLEMENT
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
Y22 AA13 AA14 AA15 AA20 AA21 AA22 AB3 W13 W14 W15 W20 W21 W22 AM12 AM15 AM20 AM23 AP11 AP17 AP19 AP24 AF1 AF2 AE4 AF3 AF4 AE5 AG1 AG2 AF5 AG3 AG4 AH1 AH3 AH4 AG5 AH2 112
BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 2 2 2 2 3 3 3 3 3 3 4
VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC PL32D PL32C PL32A PL33D PL33C PL34D PL34C PL34B PL34A PL35B PL35A PL36D PL36C PL36B PL36A PL37D
VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC VDDIO_BC PL38D PL38C PL38A PL39D PL39C PL40D PL40C PL41D PL41C PL42D PL42C PL43D PL43C PL44D PL44C PL44B
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D8 VREF_BL_01 -- D9 D10 -- VREF_BL_02 -- -- D11 D12 -- -- VREF_BL_03 D13 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 L3T_D3 L4T_D2 L5C_A0 L5T_A0 L6C_A1 L6T_A1 L7T_D0 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- COMPLEMENT TRUE TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE TRUE COMPLEMENT
L3C_D3 COMPLEMENT L4C_D2 COMPLEMENT
L7C_D0 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AJ2 AH5 AJ3 AJ4 AJ1 AK1 AK2 AJ5 AK3 AL5 AM5 AN4 AK7 AP4 AL6 AM6 AL7 AN5 AK8 AP5 AN6 AK9 AP6 AL8 AM7 AM8 AN7 AK10 AP7 AL9 AK11 AM9 AN8 AL10
BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 7 7 8 8
PL37B PL37A PL38C PL38B PL38A PL39D PL39C PL39B PL39A PB2A PB2B PB2C PB2D PB3A PB3C PB3D PB4A PB4B PB4C PB4D PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7C PB7D PB8A PB8C PB8D PB9A PB9C PB9D
PL45D PL45C PL45A PL46D PL46A PL47D PL47C PL47B PL47A PB2A PB2B PB2C PB2D PB3A PB3C PB3D PB4C PB4D PB5C PB5D PB6C PB6D PB7C PB7D PB8C PB8D PB9A PB9C PB9D PB10A PB10C PB10D PB11A PB11C PB11D
-- VREF_BL_04 -- -- -- PLL_CK7C/ HPPLL PLL_CK7T/ HPPLL -- -- DP2 -- PLL_CK6T/ PPLL PLL_CK6C/ PPLL -- -- -- VREF_BL_05 DP3 -- -- VREF_BL_06 D14 -- -- D15 D16 -- D17 D18 -- VREF_BL_07 D19 -- D20 D21
L8C_D2 COMPLEMENT L8T_D2 -- -- -- L9C_A0 L9T_A0 TRUE TRUE COMPLEMENT TRUE COMPLEMENT TRUE
L10C_D1 COMPLEMENT L10T_D1 L11T_A0 L12T_D2 TRUE TRUE TRUE
L11C_A0 COMPLEMENT
L12C_D2 COMPLEMENT -- L13T_A0 L14T_D1 L15T_D3 L16T_D2 L17T_D2 L18T_A0 -- L19T_D3 -- L20T_D1 -- L21T_D2 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
L13C_A0 COMPLEMENT L14C_D1 COMPLEMENT L15C_D3 COMPLEMENT L16C_D2 COMPLEMENT L17C_D2 COMPLEMENT L18C_A0 COMPLEMENT
L19C_D3 COMPLEMENT
L20C_D1 COMPLEMENT
AP8 BL 8 Lucent Technologies Inc.
L21C_D2 COMPLEMENT 113
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AN9 AP9 AM10 AK12 AL11 AN10 AP10 AN11 AM11 AK13 AL12 AN12 AK14 AP12 AP13 AL13 AN13 AP14 AK15 AN14 AM14 AK16 AL14 AP15 AL15 AK4 AL1 AL2 AK6 AB13 AB14 AB15 AB20 AB21 AB22 AB32 AL4 AL31 114
BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
8 8 8 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 11 11 11 11 11 11 -- -- -- -- -- -- -- -- -- -- -- -- --
PB10A PB10C PB10D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D PB15A PB15C PB15D PB16A PB16C PB16D PTEMP LVDS_R VDD33 VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS
PB12A PB12C PB12D PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D PB15C PB15D PB16C PB16D PB17C PB17D PB18C PB18D PB19A PB19C PB19D PB20A PB20C PB20D PTEMP LVDS_R VDD33 VDD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS
-- VREF_BL_08 D22 -- -- D23 D24 -- -- VREF_BL_09 D25 -- -- D26 D27 -- -- VREF_BL_10 D28 -- D29 D30 -- VREF_BL_11 D31 -- -- -- -- -- -- -- -- -- -- -- -- --
-- L22T_D1 L23T_D0 L24T_A0 L25T_A0 L26T_D0 L27T_D2 L28T_A0 L29T_A1 L30T_D3 -- L31T_D1 -- L32T_A2 -- -- -- -- -- -- -- -- -- -- -- -- --
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE -- -- -- -- -- -- -- -- -- -- -- -- --
L22C_D1 COMPLEMENT L23C_D0 COMPLEMENT L24C_A0 COMPLEMENT L25C_A0 COMPLEMENT L26C_D0 COMPLEMENT L27C_D2 COMPLEMENT L28C_A0 COMPLEMENT L29C_A1 COMPLEMENT L30C_D3 COMPLEMENT
L31C_D1 COMPLEMENT
L32C_A2 COMPLEMENT
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AM3 AM13 Y16 Y17 Y18 Y19 AA16 AA17 AK5 AL3 AM1 AM2 AM4 AN3 AP3 L4 K2 K1 L2 L3 N5 M4 M2 P5 M1 N1 N4 N2 P1 R5 P2 P3 T5 P4 R1 R2 R4
BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3
VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL PL12D PL12C PL12B PL12A PL13D PL13C PL13B PL13A PL14D PL14C PL15D PL15C PL16D PL16C PL16A PL17D PL17C PL17A PL18D PL18C PL18A PL18B
VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL VDDIO_BL PL14D PL14C PL15D PL15C PL16D PL16C PL17D PL17C PL18D PL18C PL19D PL19C PL20D PL20C PL20A PL21D PL21C PL21A PL22D PL22C PL22A PL22B
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A15 A14 -- -- VREF_CL_01 D4 -- -- RDY/BUSY/ RCLK VREF_CL_02 A13 A12 -- -- -- A11 VREF_CL_03 -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L1T_D1 L2T_D0 L3T_D1 L4C_A1 L4T_A1
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE TRUE TRUE COMPLEMENT TRUE
L1C_D1 COMPLEMENT L2C_D0 COMPLEMENT L3C_D1 COMPLEMENT
L5C_D3 COMPLEMENT L5T_D3 L6C_A2 L6T_A2 L7T_D0 -- L8C_A0 L8T_A0 -- L9T_D2 L10T_A1 TRUE COMPLEMENT TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE
L7C_D0 COMPLEMENT
L9C_D2 COMPLEMENT
L10C_A1 COMPLEMENT 115
Lucent Technologies Inc.
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function RD/MPI_STRB Pair Differential
U5 T4 T1 V5 T2 T3 U4 U3 U2 V2 V3 V4 W5 W2 W3 Y1 Y2 W4 AA1 AA2 Y5 Y4 AA3 AA5 AB1 AB2 AA4 AB4 AB5 AC1 AC2 AC5 AD2 AD3 AC4
CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL
4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 7 7 7 8 8 8 8 8
PL19D PL19C PL19A PL19B PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C PL23D PL23C PL23A PL24D PL24C PL24A PL25D PL25C PL25A PL26D PL26C PL26B PL27D PL27C PL27B PL27A PL28D PL28C PL29D PL29C PL29A
PL23D PL23C PL23A PL23B PL24D PL24C PL24B PL24A PL25D PL25C PL25B PL25A PL26D PL26C PL27D PL27C PL27A PL28D PL28C PL28A PL29D PL29C PL29A PL30D PL30C PL31D PL32D PL32C PL33D PL33C PL34D PL34C PL35D PL35C PL35A
L11C_D0 COMPLEMENT L11T_D0 L12T_D3 TRUE TRUE
VREF_CL_04 -- -- PLCK0C PLCK0T -- -- A10 A9 -- -- A8 VREF_CL_05 -- -- -- PLCK1C PLCK1T -- VREF_CL_06 A7 -- A6 A5 --
WR/MPI_RW
L12C_D3 COMPLEMENT L13C_A0 COMPLEMENT L13T_A0 L14T_A0 L15T_A0 L16T_A0 L17T_A2 L18T_D1 -- L19T_D2 -- L20T_A0 -- L21T_D3 -- L22T_A0 L23T_D3 L23T_A2 L23T_A0 -- TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE COMPLEMENT TRUE TRUE TRUE TRUE TRUE L14C_A0 COMPLEMENT L15C_A0 COMPLEMENT L16C_A0 COMPLEMENT L17C_A2 COMPLEMENT L18C_D1 COMPLEMENT
L19C_D2 COMPLEMENT
L20C_A0 COMPLEMENT
L21C_D3 COMPLEMENT
L22C_A0 COMPLEMENT L23C_D3 COMPLEMENT L23C_A2 COMPLEMENT L23C_A0 COMPLEMENT
VREF_CL_07 -- -- A4 VREF_CL_08 A3 A2 --
116
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Pin Information (continued)
Table 46. OR4E6 680-Pin PBGAM Pinout (continued)
680 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O OR4E4 OR4E6 Additional Function Pair Differential
AE1 AE2 AD4 AE3 AD5 AM22 AM32 AN1 AN2 AN33 AN34 AP1 AP2 AP18 AP33 AP34 AA18 AA19 AB16 AB17 AB18 AB19 L1 M3 R3 U1 W1 Y3 AC3 AD1
CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL
8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PL30D PL30C PL31D PL31C PL31A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL
PL36D PL36C PL37D PL37C PL37A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL VDDIO_CL
A1 A0 DP0 DP1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
L24C_A0 COMPLEMENT L24T_A0 L25T_D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRUE TRUE TRUE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L25C_D0 COMPLEMENT
Lucent Technologies Inc.
117
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Preliminary Data Sheet December 2000
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: JC = ------------------The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
TJ - TC Q
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.).
JA = ------------------TJ - TA Q
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/W.
JB
This is the thermal resistance from junction to board (JB). It is defined by: JB = ------------------where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W, and that this parameter and the way it is measured are still in JEDEC committee.
TJ - TB Q
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by:
TJ - TC JC = ------------------Q
118
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Package Thermal Characteristics
Table 47. ORCA Series 4 FPGAs Plastic Package Thermal Guidelines Package 0 fpm 352-Pin PBGA 432-Pin EBGA 680-Pin PBGAM 19.0 11.0 14.5
JA (C/W)
200 fpm 16.0 8.5 TBD 500 fpm 15.0 7.5 TBD
T = 70 C Max, TJ = 125 C Max 0 fpm (W) 2.9 5.0 3.8
Package Coplanarity
The coplanarity limits of the Lucent packages are as follows:
s s s
PBGA: 8.0 mils EBGA: 8.0 mils PBGAM: 8.0 mils
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 48 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m . The parasitic values in Table 48 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Table 48. ORCA Series 4 FPGAs Package Parasitics Package Type 352-Pin PBGA 432-Pin EBGA 680-Pin PBGAM LSW 5 4.0 3.8 LMW 2 1.5 1.3 RW 220 500 250 C1 1.5 1.0 1.0 C2 1.5 1.0 1.0 CM 1.5 0.3 0.3 LSL 7--12 3.0--5.5 2.8--5 LML 3--6 0.5--1 0.5--1
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Package Parasitics (continued)
LSW PAD N
RW
LSL
CIRCUIT BOARD PAD
C1 LMW CM LML
C2
PAD N + 1 LSW RW C1 LSL C2
5-3862(C)r2
Figure 47. Package Parasitics
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.
120
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Package Outline Drawings
352-Pin PBGA
Dimensions are in millimeters.
35.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 30.00 -0.00
+0.70 30.00 -0.00 35.00 0.20
MOLD COMPOUND PWB 0.56 0.06 1.17 0.05 2.33 0.21 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.27 = 31.75
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25
0.75 0.15
25 SPACES @ 1.27 = 31.75
CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) (SEE NOTE BELOW) A1 BALL CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.
Lucent Technologies Inc.
121
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Package Outline Drawings (continued)
432-Pin EBGA
Dimensions are in millimeters.
40.00 0.10 A1 BALL IDENTIFIER ZONE
40.00 0.10
0.91 0.06
1.54 0.13 SEATING PLANE 0.20
0.63 0.07
SOLDER BALL
30 SPACES @ 1.27 = 38.10
AL AK AH AG AF AD AB Y V U T P M K H F D C B A R N L J G E AE AC AA W AJ
0.75 0.15
30 SPACES @ 1.27 = 38.10
A1 BALL CORNER
1 2
3 4
5 6
7 8
9 10
11 12
13 15 17 19 21 23 25 27 29 31 14 16 18 20 22 24 26 28 30
5-4409(F)
122
Lucent Technologies Inc.
Preliminary Data Sheet December 2000
ORCA Series 4 FPGAs
Package Outline Drawings (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00
+ 0.70
35.00
30.00 - 0.00
+ 0.70
1.170 0.61 0.08 SEATING PLANE 0.20 SOLDER BALL 0.50 0.10 33 SPACES @ 1.00 = 33.00 2.51 MAX
AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34
0.64 0.15
33 SPACES @ 1.00 = 33.00
A1 BALL CORNER
5-4406(F)
Lucent Technologies Inc.
123
ORCA Series 4 FPGAs
Preliminary Data Sheet December 2000
Ordering Information
OR4Exx -1 BM 680 DEVICE TYPE SPEED GRADE NUMBER OF PINS PACKAGE TYPE
5-6435 (F)
Table 49. Series 4 Package Matrix (Speed Grades) Packages OR4E2 OR4E4 OR4E6 OR4E10 Table 50. Package Options Symbol BA BC BM Description Plastic Ball Grid Array (PBGA) Enhanced Ball Grid Array (EBGA) Plastic Multilayer Ball Grid Array (PBGAM) 352-Pin PBGA 1.27 mm -1/-2 -1/-2 -1/-2 -- 432-Pin EBGA 1.27 mm -1/-2 -1/-2 -1/-2 -- 680-Pin PBGAM 1 mm -- -1/-2 -1/-2 -1/-2
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
December 2000 DS01-024NCIP (Replaces DS00-221FPGA)

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